cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
srdjan.opacic
Adventurer
Adventurer
632 Views
Registered: ‎08-21-2017

Maximum skew on 8x GTX TX

Hi everyone,

I'm trying to find out maximum possible skew caused by TX buffer, in order to decide should I bypass it or not. I expect that maximum possible skew is defined by depth of this buffer, or? My interface uses 2 full quads, with inputs completely aligned/synchronized to the same clock.

Thanks

Srdjan

0 Kudos
5 Replies
roym
Moderator
Moderator
577 Views
Registered: ‎07-30-2007

Yes, In theory the depth of the TX buffer indicates the maximum skew you might see.  I think in practice the skew would rarely if ever get more than 2 usrclk cycles out of alignment through that buffer if the resets are handled properly.  Any temperature drift would tend to send the channel's skew in the same direction.




----------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution
Be sure to visit the Resources post periodically to keep up with the latest
https://forums.xilinx.com/t5/Serial-Transceivers/Serial-Transceiver-Forum-Guidelines-and-Useful-Resources/td-p/1173590
----------------------------------------------------------------------------


0 Kudos
srdjan.opacic
Adventurer
Adventurer
539 Views
Registered: ‎08-21-2017

Hi @roym ,

Thanks for the reply, can you tell me what is the depth of TX buffer? I can't seem to find that number anywhere.

Best regards

Srdjan

0 Kudos
srdjan.opacic
Adventurer
Adventurer
514 Views
Registered: ‎08-21-2017

I just received info that my skew on TXD data pairs has to be below 15UI. My internal data bus is 16-bit, i use 8B10B conversion, so when you say max 2 user clocks, that would translate to 40 UI, correct? Can this skew be reduced to 0 by using RX BUFFER bypass (because just one user clock would translate to 20UI)?

Thanks

Srdjan

0 Kudos
roym
Moderator
Moderator
449 Views
Registered: ‎07-30-2007

In that case you don't want to use the TX buffer. 2 userclks is 40 ui and it is possible for it to be higher.  If you bypass the TX buffer the TX skew will be limited to 500 ps. I answer your question for sure without knowing your line rate.  I believe this is less than 15ui at the max GTX speed so you will be good.




----------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution
Be sure to visit the Resources post periodically to keep up with the latest
https://forums.xilinx.com/t5/Serial-Transceivers/Serial-Transceiver-Forum-Guidelines-and-Useful-Resources/td-p/1173590
----------------------------------------------------------------------------


0 Kudos
srdjan.opacic
Adventurer
Adventurer
397 Views
Registered: ‎08-21-2017

Hi @roym ,

Thanks, this sounds like it would be acceptable for me. My line rate is currently 2.97 Gbps, so one UI is 336.7 ps. I agree, even if my line rate increases, this should be sufficient.

Best regards

Srdjan

0 Kudos