10-29-2019 05:06 AM
I'm trying to find out maximum possible skew caused by TX buffer, in order to decide should I bypass it or not. I expect that maximum possible skew is defined by depth of this buffer, or? My interface uses 2 full quads, with inputs completely aligned/synchronized to the same clock.
10-30-2019 08:53 AM
Yes, In theory the depth of the TX buffer indicates the maximum skew you might see. I think in practice the skew would rarely if ever get more than 2 usrclk cycles out of alignment through that buffer if the resets are handled properly. Any temperature drift would tend to send the channel's skew in the same direction.
11-07-2019 12:44 AM
I just received info that my skew on TXD data pairs has to be below 15UI. My internal data bus is 16-bit, i use 8B10B conversion, so when you say max 2 user clocks, that would translate to 40 UI, correct? Can this skew be reduced to 0 by using RX BUFFER bypass (because just one user clock would translate to 20UI)?
11-15-2019 10:32 AM - edited 11-15-2019 12:32 PM
In that case you don't want to use the TX buffer. 2 userclks is 40 ui and it is possible for it to be higher. If you bypass the TX buffer the TX skew will be limited to 500 ps. I answer your question for sure without knowing your line rate. I believe this is less than 15ui at the max GTX speed so you will be good.
11-18-2019 12:16 AM
Hi @roym ,
Thanks, this sounds like it would be acceptable for me. My line rate is currently 2.97 Gbps, so one UI is 336.7 ps. I agree, even if my line rate increases, this should be sufficient.