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Observer khal
Observer
887 Views
Registered: ‎03-03-2017

Mixing Protocols on Transceiver TX and RX

We are contemplating 3 different designs with a Kintex-7 160T device in a -3E speed grade with 8 GTX transceivers and looking for feedback. All 3 options involve using one protocol on the RX lines and a different protocol on the TX lines of the GTXs - I am trying to determine if these will be feasible to implement: (the TX is the same in all 3 scenarios)

 

Design #1:

- TX on 4 GTXs used to interface the Xilinx JESD204B IP core to a DAC, at line rates of 10.0 Gbps

- TX on other 4 GTXs used to interface the Xilinx JESD204B IP core to a second DAC, at line rates of 10.0 Gbps

- RX on all 8 GTXs used to interface the Xilinx JESD204B IP core to an ADC, at line rates of 12.5 Gbps

 

 

Design #2:

- TX on 4 GTXs used to interface the Xilinx JESD204B IP core to a DAC, at line rates of 10.0 Gbps

- TX on other 4 GTXs used to interface the Xilinx JESD204B IP core to a second DAC, at line rates of 10.0 Gbps

- RX on 1 of these GTXs used to implement receive-only 10GbE using Xilinx 10GEMAC IP (10GBASE-SR, i.e. 10.3125 Gbps)

 

Design #3:

- TX on 4 GTXs used to interface the Xilinx JESD204B IP core to a DAC, at line rates of 10.0 Gbps

- TX on other 4 GTXs used to interface the Xilinx JESD204B IP core to a second DAC, at line rates of 10.0 Gbps

- RX on 4 of these GTXs used to implement receive-only 40GbE using Xilinx 40G/50G Subsystem IP (40GBASE-SR4, i.e. 4 x 10.3125 Gbps)

 

Questions:

 

1) Will Vivado allow implementation of such designs? Any guidelines (user guides, app notes, etc) on how to mix RX and TX protocols on a GTX transceiver?

 

2) Any concerns with clocking? Since there are 2 transceiver quads, I assume that a QPLL on 1 quad could be used for the RX protocols and a QPLL on the adjacent quad could be used for the TX protocols - correct?

 

3) Any major concerns with PCB layout?

 

4) With regards to the 10GbE or 40GbE receive-only interfaces - interface will be point-to-point (i.e. no network switches), intention is to use static ARP table (therefore no response needed back on transmitter for ARP resolution) and packets received on the FPGA will all be UDP. Not sure if the physical layer protocols require any bi-directional training sequences (which would be problematic). Also, plan to use SFP modules, not sure if the modules themselves require bi-directional traffic for proper implementation.

 

Any feedback would be greatly appreciated.

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2 Replies
Adventurer
Adventurer
845 Views
Registered: ‎02-06-2012

Re: Mixing Protocols on Transceiver TX and RX

AFAIK 10GbE uses a link training, so if the other end of your 10G link is a PC you may have problems getting "link up" status.

Using different line rates for TX/RX is definitely possible. I did that in the past, albeit in a CPLL/QPLL combo.
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Xilinx Employee
Xilinx Employee
830 Views
Registered: ‎06-01-2017

Re: Mixing Protocols on Transceiver TX and RX

To answer question #2:

2) Any concerns with clocking? Since there are 2 transceiver quads, I assume that a QPLL on 1 quad could be used for the RX protocols and a QPLL on the adjacent quad could be used for the TX protocols - correct?

 

The input MGTREFCLK can be shared over multiple quads (up to 2 quads up/down). The QPLL output clock cannot. The QPLLs can only feed clocks to the GTs in the same quad. However, it is possible to drive TX and RX with different rates, either by using the same QPLL, or by using QPLL and CPLL. Have you tried setting up your desired rates/configuration in the GT wizard?

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