Multi-lane GTX Transmitter Alignment

[nlantz]

I have an application that requires four parallel channels which transmit 10 Gbps each. These channels must have a deterministic skew offsets between them to within 100 ps.  

The 7 Series FPGAs GTX/GTH Transceivers User Guide suggests that I can accomplish this with a GTX by bypassing the Tx Buffer (pg 136). I have implemented this on the VC707 platform. 

When implemented, I observe three of the four channels have a deterministic skew offset, while one channel has a random offset plus or minus about 200ps. The random skew changes at power up, reprogramming and soft reset of the IP.  This is curious because 3 of the four channels perform as expected and all channels are implemented identically and clocked from the same QPLL. The implementatin is being run in manual mode, however the required allignment ports (Fig 3-23) are not present on the IP so this procedure was not implemented. However the channels do not need to be alligned, they just need a known skew between them, so this may not be necessary anyway. 

Some images of my IP configuration are below. 

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Is it possible to implement 4 GTX channels with deterministic skew? They do not need to be alligned. I just need a known offset.  

I am happy to provide more information if requested. 

Thank you for the help!

[roym · Accepted solution]

They spec lane to lane skew in the data sheet as 500ps, I believe, and that is when you do buffer bypass.   To get a determinate skew you would need to leave the buffer enabled and use the lane TX phase interpolator to zero out the skew.  This isn't really supported and you would likely need to spend quite a bit of time debugging.  GT's were not really meant to keep low skew and have channel bonding circuitry to get around this problem.