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Observer
Observer
741 Views
Registered: ‎04-17-2020

### No 53G Links with IBERT GTM on VCU129 ###

Dear Xilinx Team,

I have 2 issues regarding the IBERT with the GTM transceivers and external loopback adapters on the VCU129 eval board under Vivado 2019.2.

For now I'm just using the dual GTM 120.

First, as opposed to documentation and unlike GTY IBERT, in the clock settings tab of the GTM IBERT GUI
it is not possible to use a transceiver refclk as IBERT sysclk. Only "External" sysclk is selectable. Why is that ?

This is a problem as I'm unable to find a suitable clock source on the VCU129. Digging through the PCB schematics

the only candidate seems to be the CLK_OUT SI5428_4_CH5. But I suppose it's not running at the default 156.25MHz

like the other GT ref clocks and I don't know how to program it. 

On the ZCU111 board this was easy, a suitable clock is present here.

So I tried several attempts to patch the toplevel GTM IBERT IP example design SV file and XDC.

The idea is to feed the div2 output from internal ref clock buffer through another buffer as sys clk into the IBERT core thus

getting rid of an external sysclk for the IBERT core.

However at best I get unstable links in the Serial IO Analyzer or no link at all.

With this I wonder how anybody could have achieved a running IBERT on VCU129 yet ??

Can you give me a workaround, how I have to make the patches exactly ?

    ThanX a lot            Oliver Hauck

 

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Moderator
Moderator
675 Views
Registered: ‎07-30-2007

XTP559 has utilities for programming the clocks on the board.  I think this should get you going. 




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Moderator
Moderator
655 Views
Registered: ‎10-19-2011

IBERT system clock requires the source to be free running. I think that is likely the issue with the clocks you have selected, its not free running and has some startup logic associated with it. To elaborate a little on what Roy say, you can use the xtp559 to program the clocks. You will need to open the zip and at the bottom of the BIT there is something called the "system controller". This tab will have a program clocks selection where you can configure many of the programmable clocks on the board through files or directly writing frequencies to them.

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Observer
Observer
629 Views
Registered: ‎04-17-2020

Hello,

thanx for the answers, I'll try this and come back to you.

But: why is it possible to use a transceiver ref clk as IBERT sys clk

in GTY IBERT GUI (and it works with GTY on VCU129), but not

in GTM IBERT GUI ? Those ref clocks are free running after all.

 

  See you Oliver

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Observer
Observer
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Registered: ‎04-17-2020

Gentlemen,

I'm back, to no avail. I tried the external clock, GTM IBERT is found on the HW, but still got no link.

As I understand it the only possibility is to use clock from SI5348 #4 (U21 in schematic) channel 5, 

which is AC coupled to FPGA pads R32 (P) and R33 (N). I measured the 156.25MHz clock being

present on the VCU129 board right after SMD caps C1617 and C1618.

So what"s wrong here ? Btw. my IBERT tests in the VCU129 BIT were also fail.

Now I'm losing a lot of time with this. It would be a great help if you could really play this through

end-to-end at your side so that I have an example design that is guaranteed to work. 

I'm wondering why nobody else has any ISSUES with IBERT GTM on VCU129 ?

It would be a lot easier if one could use an internal clock for IBERT sys clk, as is possible

in GTY IBERT GUI which allows using transceiver ref clk. Why is this not possible for GTM ?

Looking forward to your expert advice, Best Oliver

IBERT_GTM_clk_settings.PNG
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Observer
Observer
527 Views
Registered: ‎04-17-2020

## Note: My original post has been moved from Serial Transceiver Board to Eval Boards,

then reappearing in Serial Transceivers, so I repost it here again ##

 

Gentlemen,

I'm back, to no avail. I tried the external clock, GTM IBERT is found on the HW, but still got no link.

As I understand it the only possibility is to use clock from SI5348 #4 (U21 in schematic) channel 5, 

which is AC coupled to FPGA pads R32 (P) and R33 (N). I measured the 156.25MHz clock being

present on the VCU129 board right after SMD caps C1617 and C1618.

So what"s wrong here ? Btw. my IBERT tests in the VCU129 BIT were also fail.

Now I'm losing a lot of time with this. It would be a great help if you could really play this through

end-to-end at your side so that I have an example design that is guaranteed to work. 

I'm wondering why nobody else has any ISSUES with IBERT GTM on VCU129 ?

It would be a lot easier if one could use an internal clock for IBERT sys clk, as is possible

in GTY IBERT GUI which allows using transceiver ref clk. Why is this not possible for GTM ?

Looking forward to your expert advice, Best Oliver

 
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IBERT_GTM_clk_settings.PNG
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Xilinx Employee
Xilinx Employee
469 Views
Registered: ‎06-01-2017

Hi @Oliver_Hauck 

R32 should be a correct clock to use for IBERT system clock. Are you able to get link-up if you do near-end PCS or near-end PMA loopback?

Are you using the loopback module plugged into QSPDD2 connector? I have a VCU129 in a similar setup. If you have a bitfile I could try on my board.

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Observer
Observer
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Registered: ‎04-17-2020

 
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Observer
Observer
231 Views
Registered: ‎04-17-2020

Dear @jhua ,

 

took me some time to come back. As IBERT IP is encrypted I could not use it as originally intended and had to invent my own stuff. But I still need for the next stept to get GTM IBERT running so I include here for VCU129 .bit and .ltx and GTM IBERT wizard options. I could not get a stable link with this, so it would be great if you could give it a try.

 

ThanX Oliver

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Xilinx Employee
Xilinx Employee
216 Views
Registered: ‎06-01-2017

Hi @Oliver_Hauck 

Can you clarify on what exact manual modifications that you had to make on top of the IBERT IP for it to work with your hardware? This can help understand what the issues may lie. On the VCU129, the default IBERT IP should work.

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Xilinx Employee
Xilinx Employee
150 Views
Registered: ‎06-01-2017

Hi @Oliver_Hauck 

I programmed with your .bit and .ltx onto my VCU129, and the link is up and running error free. This is with loopback module plugged into QSFPDD2.

jhua_0-1601510303588.png

I set the loopback mode to NE PCS loopback and it is also error free.

jhua_1-1601510434069.png

Which setup are you running?

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