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jeffrey.johnson
Voyager
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Registered: ‎02-07-2008

Override LOC constraint on gigabit transceivers

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Hi,

 

I have a PCIe design for the KCU105 board in which I need to swap two GTs in a single Quad. The PCIe IP (AXI PCIe Bridge for Gen3) has its own built-in LOC constraints for these GTs, and it seems that my own LOC constraints will not override them. I get an error saying that the GTs can't be placed in such-and-such location because another is already placed there (by the built-in constraints).

 

Does anyone know how I can get around these built-in LOC constraints and apply my own?

 

Thanks.

 

Jeff

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jeffrey.johnson
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Registered: ‎02-07-2008

@hongh

 

Thanks for your reply. Unfortunately, I can't use reset_property LOC in the constraints (.xdc) file, so this didn't turn out to be a solution for me. Instead, I used set_property LOC to shuffle the GTs around and get the placement that I needed. For example, to swap GTs A and B in positions X0Y0 and X0Y1 respectively, I first move GT A to an unused LOC, say X0Y2, then I can place GT B to X0Y0, then I move GT A into X0Y1. It's not elegant, but it works and it's a simple change to my constraints file.

 

# if GT A has been placed at X0Y0, and GT B at X0Y1,
# you can swap their placement by doing the following:

set_property LOC GTHE3_CHANNEL_X0Y2 [get_cells {GT A}]
set_property LOC GTHE3_CHANNEL_X0Y0 [get_cells {GT B}]
set_property LOC GTHE3_CHANNEL_X0Y1 [get_cells {GT A}]

# This assumes that X0Y2 is an unused location

 

Jeff

 

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venkata
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Registered: ‎02-16-2010
Are you trying to generate an x2 design and reverse the lane assignment to GT's?
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jeffrey.johnson
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Registered: ‎02-07-2008

@venkata

 

No, I've got a x4 lane design and I need to swap lanes 1 and 2. Lanes 0 and 3 will stay on the default (optimal) GTs. All lanes are in the same Quad.

 

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hongh
Moderator
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Registered: ‎11-04-2010

Hi, @jeffrey.johnson ,

You can use "reset_property LOC   [get_cells Your_gt_cells]" to clear the original GT LOC and then apply your own GT LOC in the top XDC.

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jeffrey.johnson
Voyager
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Registered: ‎02-07-2008

@hongh

 

Thanks for your reply. Unfortunately, I can't use reset_property LOC in the constraints (.xdc) file, so this didn't turn out to be a solution for me. Instead, I used set_property LOC to shuffle the GTs around and get the placement that I needed. For example, to swap GTs A and B in positions X0Y0 and X0Y1 respectively, I first move GT A to an unused LOC, say X0Y2, then I can place GT B to X0Y0, then I move GT A into X0Y1. It's not elegant, but it works and it's a simple change to my constraints file.

 

# if GT A has been placed at X0Y0, and GT B at X0Y1,
# you can swap their placement by doing the following:

set_property LOC GTHE3_CHANNEL_X0Y2 [get_cells {GT A}]
set_property LOC GTHE3_CHANNEL_X0Y0 [get_cells {GT B}]
set_property LOC GTHE3_CHANNEL_X0Y1 [get_cells {GT A}]

# This assumes that X0Y2 is an unused location

 

Jeff

 

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hongh
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Registered: ‎11-04-2010

Hi, @jeffrey.johnson ,

It is well that the current constraints can work properly for you.

 

When there are more GTs with LOC from IP catalog, it maybe involve issue.

The LOC constraints will not be used in synthesis, So you can also consider the below method as a backup for you:

<1> Add XX.tcl in the TCL.POST in settings of synthesis.

<2> The content in XX.tcl:

     reset_property LOC [get_cells -hier -filter {REF_NAME =~ *GT }]

     read_xdc ./GY_LOC.xdc

 

 

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minxu
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Registered: ‎03-27-2017
I am trying to use the Synthesis tcl.post solution you proposed, however, synthesis then failed due to reset_property LOC [get_cells ...] resulted in no objects for the reset_property command to act on. I moved the tcl command to the Implementation Init Design tcl.pre step. Implementation failed due to no project open. So then the command is moved to tcl.post step of the Init Design phase. At this point, the command took and the changes are applied but there is a warning that the changes are not permanent, and it is advised to use Unmanaged tcl scripts.
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