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Visitor
Visitor
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Registered: ‎07-05-2014

PCIe Lane Location

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I need to change the lane assignment in a PCIe design from the one created by the IP.  My previous engineer made the changes and it worked fine.  We now upgraded the PCIe IP and it generated a new constraints file with the default lane locations.  In the previous version of Vivado (2017.3) he edited the generated file but on the new version (2018.2) we can't figure out how to do it.

On Vivado 2018.2, how do you change the assignment of the PCIe lanes?

 

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Xilinx Employee
Xilinx Employee
936 Views
Registered: ‎08-07-2007

hi @shalomkattan

 

if you wanted to change the default pin assignment, you can use an text editor to modify the LOC constraints for GT CHANNELs in the *.gt.xdc file.

Below is the snapshot.

 

Please keep in mind that the default pinout is recommanded for PCIe. If you don't use the default, you need to make sure timing closure.

 

Thanks,

Boris

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pcie_loc.png
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Xilinx Employee
Xilinx Employee
937 Views
Registered: ‎08-07-2007

hi @shalomkattan

 

if you wanted to change the default pin assignment, you can use an text editor to modify the LOC constraints for GT CHANNELs in the *.gt.xdc file.

Below is the snapshot.

 

Please keep in mind that the default pinout is recommanded for PCIe. If you don't use the default, you need to make sure timing closure.

 

Thanks,

Boris

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pcie_loc.png
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Visitor
Visitor
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Registered: ‎07-05-2014

Your answer seems to be for the Ultrascale.  My design is on an Artix 7:

IP Name:  7 Series Integrated Block for PCI Express

Version: 3.3 (Rev 6)

I attach a screenshot of the sources.  My PCIe IP has a .dcp file.

 

PCIe_Sources.PNG
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Xilinx Employee
Xilinx Employee
910 Views
Registered: ‎08-07-2007

hi @shalomkattan

 

thanks for notice with device family.

similarly you can edit the xdc file as below snapshot shown.

 

Thanks,

Boris

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7s.png
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Registered: ‎05-09-2016

Hi,@

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