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Registered: ‎12-06-2017

PCIe lane order

For a x16 PCIe Gen3 routing, does ultrascale support lane order reversal within a Quad.

For example, a x16 pcie spanning Banks 220-223, with PCIe lane0 thru 3 in Bank 223, lanes 4-7 in Bank222, lanes 8-11 in Bank221, lanes 12-15 in Bank220. 

All the lanes are in order - Lane0 connecting to P0/N0, Lane1 to P1/N1, Lane2 to P2/N2, Lane3 to P3/N3 in a bank.

To simplify routing:

Can I change the lane order within a Bank?

Can I swap lanes from one bank to another?

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3 Replies
Registered: ‎02-24-2014

For a 16 Lane interface, lane reversal is only supported for a full 16 lanes.  See page 268 (Lane Reversal) in pg213.     


In general, lane reversal is only supported for 2, 4, 8, or 16 lane interfaces, and doesn't work if downshifting is needed.    In general, the downshifting requirement is a pretty good argument for not reversing the lanes on your board design.    i.e.   Reversing your board layout prevents downshifting from working properly. 


However...   Since the connections between the GTH/GTY and the PCI-E block are using the FPGA routing, you should be able to swap lanes within some reasonable limits, and these limits are determined by the distance between the GTH/GTY and the PCI-E block.   There are no hard and fast limits, only the ones imposed by the ability of the Vivado router to meet the setup timing when connecting these blocks.     As a rule of thumb, swapping lanes within a Quad should generally be safe.   It's probably ok as well to swap between adjacent quads.   I have seen timing failures when the placer accidently put the PCI-E block in the wrong site, which was far away from the transceiver sites.   So to be safe,  validate your place & route timing before freezing your board layout.

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Xilinx Employee
Xilinx Employee
Registered: ‎08-01-2008

For 7-Series when the IP is configured for Root Port Configuration, the Enable Lane Reversal option is disabled by default. However if you configure the IP for an End Point configuration, you can enable this option. There is a parameter DISABLE_LANE_REVERSAL that is set to a default value in the IP generated files. When we do a search for DISABLE_LANE_REVERSAL in 7-Series generated files, we do see that the parameter is set to TRUE in the core_top.v file and is set to TRUE in pcie_7x and pcie_top files. Since the hierarchy of the files is in the following order core_top -> pcie_top -> pcie_7x, this would mean that the hard block does have support for lane reversal however the IP does not allow for this option. To do a lane reversal we have to modify the DISABLE_LANE_REVERSAL parameter to FALSE in the core_top.v however this would not be a tested/supported configuration.
For Ultrascale devices, this is supported by default in both configurations. Hence this is enabled by default and therefore this parameter does not exist.
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Xilinx Employee
Xilinx Employee
Registered: ‎08-07-2007



yes, if timing can be met. you need to manually change the xdc for pin location or GT location according to the hardware board.


Xilinx recommanded to use default pinout because it can meet timing easily.


by Xilinx default setting, PCIe lane 0 is placed in the top-most GT of the top-most GT Quad (as shown in
Vivado Integrated Design Environment (IDE) Device view). Subsequent lanes use the next
available GTs moving vertically down the device as the lane number increments. This means
that by default the highest PCIe lane number uses the bottom-most GT in the bottom-most
GT Quad that is used for PCIe.

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