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Registered: ‎03-24-2019

PCS for 10GBASE-T Protocol

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According to the diagram below, 10GBASE-T require "LDPC PCS".
May I know does Xilinx support this? It should be 64B/65B encoding and decoding, right?

Any available Xilinx IP for that?

 

10g.PNG

 

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Registered: ‎01-08-2012

You need an external PHY for any of the xxBase-T copper Ethernet interfaces.  These use specialised analog cable drivers and receivers, etc. that aren't found in the high speed transceivers from Xilinx (or any FPGA manufacturer, for that matter).

For 1000Base-T and faster, the PHY contains a massive amount of DSP for equalisation and NEXT cancellation.  In theory, you could do some of that in an FPGA + ADCs + DACs, but a dedicated PHY chip will do it for a fraction of the cost, board space and power.

10GBase-T PHYs have only been around for a few years.  There are relatively few manufacturers.  I believe Aquantia were the first, but today you'd be more likely to use a part from Broadcom or Marvell or Intel.

 

OTOH, if you have an optical interface such as SFP+, it will connect directly to an FPGA transceiver without needing any extra circuitry.

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Registered: ‎01-08-2012

In the context of 10GbE, I believe that LDPC (which is a type of FEC) is only used with 10GBase-T.  Since you will only be connecting to 10GBase-T through an external (i.e. not-in-the-FPGA) PHY, and the external PHY takes care of the FEC, there is no need to perform this FEC function inside the FPGA.  Hence, there is no IP core for it in Xilinx's catalogue of 10G Ethernet products.

The drawing you posted looks like it's from IEEE802.3 and does not represent reality.  You should treat it more as a reference model than an implementation guide.

The FPGA will require a MAC, and that MAC will interface to the PHY over an interface such as USXGMII, XFI, RXAUI, etc.  In practice, no designer uses XGMII.

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Registered: ‎03-24-2019

@allanherriman & @karnanl , Could you please enlighten me why must 10GBase-T implemented through external PHY? Any specific reason why Xilinx PHY don't support it? I just don't get it.

I apologize if you find this question is not appropriate.

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Registered: ‎01-08-2012

You need an external PHY for any of the xxBase-T copper Ethernet interfaces.  These use specialised analog cable drivers and receivers, etc. that aren't found in the high speed transceivers from Xilinx (or any FPGA manufacturer, for that matter).

For 1000Base-T and faster, the PHY contains a massive amount of DSP for equalisation and NEXT cancellation.  In theory, you could do some of that in an FPGA + ADCs + DACs, but a dedicated PHY chip will do it for a fraction of the cost, board space and power.

10GBase-T PHYs have only been around for a few years.  There are relatively few manufacturers.  I believe Aquantia were the first, but today you'd be more likely to use a part from Broadcom or Marvell or Intel.

 

OTOH, if you have an optical interface such as SFP+, it will connect directly to an FPGA transceiver without needing any extra circuitry.

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Registered: ‎03-24-2019

@allanherriman , Thanks for the  explanation on the 10GBASE-T PHY

In summary, an external PHY (say Marvell chip) is needed for 10GBASE-T & the LDPC decoding should be handled by the external PHY as well.

On the other hand, i have FPGA talking to the Marvell chip, it probably just a standard transceiver interface such as RXAUI (Using two 6.25 Gbps line rate to achieve 10-Gbps data rate).

Marvell.PNG

However, do i need USXGMII IP in my FPGA?
Xilinx seem like offering a licensing core IP --> USXGMII to support 10GBase-T application.

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Registered: ‎01-08-2012

USXGMII is an alternative to RXAUI.  If you have RXAUI, you do not need USXGMII.

But that diagram also shows XFI (which uses one transceiver at 10.3125Gb/s, vs two for RXAUI).  If you only need to support 10G rates, XFI would be fine, particularly as the regular (free?) MAC + transceiver core probably supports that already.  (Assuming your FPGA has 10G transceivers.)

If you need rate agility (e.g. switching between 10G, 5G, 2.5G, 1G, 100M etc.) then USXGMII is probably the interface to use.  USXGMII, like XFI, also uses a single transceiver at 10.3125Gb/s, but changes the encoding by repeating symbols to achieve the lower data rates, much the same way that SGMII does to switch between 10M/100M and 1G rates.