PS-GTR reference clock question when using GEM and GT lane.

[caballes]

Hi,

I'd like to use the 1 GEM in the Zynq Ultrascale+ for 1G Ethernet via SGMII.
Let's say I plan on using the GT Lane0 (PS-GTR), instead of EMIO or MIO pins.
Bank 505 has all the relevant signals: Differential Tx and Rx Data and Reference clock input.

I'm not exactly sure what to do with the reference clock input.  I know it needs a 125MHz clock.
I've seen reference designs on RGMII implementation where a dedicated clock chip is used to generate the 125MHz.
Haven't really found a reference design using the GEM with gigabit transceiver.

So here's the question(s):
(1) When using the GEM and PS-GTR, do I need to provide a 125MHz clock from an external source? I think this is the case.

This is what's throwing me off.
(2) In Vivado, within the Ultrascale clock configuration, Output Clocks,
I see that a 125MHz clock is automatically generated for "Gem0" in the Peripherals/IO Clock tab. - It's an output.
Where is this going? Is this internally connected to the MGTREFCLK input that I'm using?

Thanks,
Darwin

[roym · Accepted solution]

Internal clocks are not clean enough in terms of jitter to be capable of driving GT's.  Making the internal clocks  that clean would be way too expensive and is not needed for driving the fabric logic.  No internal clock either one that is there already or one you generate can be used.  You must have a clean external clock driving those dedicated reference clock pins I'm afraid.

[danstallman]

Any way to get ahold of Caballes? I need info on using the GEM and SGMII.