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mcoopwood
Visitor
Visitor
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Registered: ‎10-04-2019

PS-GTR termination, Vcmin?

I'm designing a PC board for the UltraScale+ MPSoC. Just looking for a sanity check with respect to the common mode input voltage (Vcmin) of UltraScale+ GTR receivers. DS925 Table 56 says it's 0V (typ) but there is no min or max. Shouldn't Vcmin=Vcmout so that the transmitters and receivers are level-compatible, and to enable loop-back testing? It appears that Vcmin=Vcmout for GTH transceivers. I don't understand why GTR transceivers are different. Questions:

1. Is direct coupling allowed, or AC coupling only? Is there a minimum data rate?

2. Are the GTR inputs terminated through 50ohms to 0V (GND)? If not, what voltage are they terminated to? Do these terminations feature Digitally Controlled Impedance?

3. If I'm using the Tx but not the Rx of a given tranceiver, can I tie the unused Rx inputs to ground? Leave them floating? Short them together and let Vcm float? Terminate them through 50ohms to a rail, or ground? Pull them in opposite directions to prevent the receiver from oscillating? Are the inputs already biased slightly apart internally?

4. I assume single-ended use is not recommended, but what if I need to drive an Rx input single-ended and direct coupled? How would I know how to bias the unused half of the diff-pair?

5. What does the driver and receiver topology and termination scheme look like at the resistor and transistor level?

High speed digital hardware designers need to know these kinds of details. Now that Xilinx serial tranceivers are entering the high speed realm, it would be good to regard them as more than generic "black box" buffers. I feel like I've scoured DS891, DS925, UG571, UG576, UG583, and UG1085. If anyone can point me towards some better resources on GTR and GTH transceiver hardware, I would really appreciate it :-)

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karnanl
Xilinx Employee
Xilinx Employee
485 Views
Registered: ‎03-30-2016

Hello @mcoopwood 

Answered some of your questions.


>1. Is direct coupling allowed, or AC coupling only? Is there a minimum data rate?

AC coupling is required. See also
https://www.xilinx.com/support/answers/65375.html
https://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf (CHapter4)

Minimum datarate=1.25Gbps. See also DS925 Table 58
https://www.xilinx.com/support/documentation/data_sheets/ds925-zynq-ultrascale-plus.pdf

>2. Are the GTR inputs terminated through 50ohms to 0V (GND)?

Yes

> Do these terminations feature Digitally Controlled Impedance?

No. See also
https://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf (CHapter4)


>3. If I'm using the Tx but not the Rx of a given tranceiver, can I tie the unused Rx inputs to ground? Leave them floating?
>Short them together and let Vcm float? Terminate them through 50ohms to a rail, or ground? Pull them in opposite directions to prevent the receiver from oscillating?
>Are the inputs already biased slightly apart internally?

See the following AR for unused RX.
https://www.xilinx.com/support/answers/65375.html
https://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf (CHapter4)

>4. I assume single-ended use is not recommended,

Yes your understanding is correct.

>but what if I need to drive an Rx input single-ended and direct coupled? How would I know how to bias the unused half of the diff-pair?

Single-ended and DC coupled is not supported.

>5. What does the driver and receiver topology and termination scheme look like at the resistor and transistor level?

Hmm, I think this kind of information is not released for public

Thanks & regard
Leo


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