Partially routed net error in GTH transceiver clock

[verilog_bee]

Hello,

The error comes during generating a bitstream.

Attached  :

Error in vivado shows vivado error.

imp_runme is a log file of implementation.

synthesized netlist for mgtref clk & one pll instantiated in design. 

cm0_gtreclk00_int : where actual error comes in generating bitstream file.

please guide. 

[eschidl · Accepted solution]

Hi @verilog_bee ,

the PLL input should be connected to IBUFDS_GTE3/ODIV2. It cannot be connected to IBUFDS_GTE3/O.