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verilog_bee
Adventurer
Adventurer
571 Views
Registered: ‎11-23-2018

Partially routed net error in GTH transceiver clock

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Hello,

The error comes during generating a bitstream.

Attached  :

Error in vivado shows vivado error.

imp_runme is a log file of implementation.

synthesized netlist for mgtref clk & one pll instantiated in design. 

cm0_gtreclk00_int : where actual error comes in generating bitstream file.

please guide. 

 

Error_in_vivado.png
synthesized_netist.jpg
cm0_gtrefclk00_int.jpg
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1 Solution

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eschidl
Xilinx Employee
Xilinx Employee
527 Views
Registered: ‎10-19-2011

Hi @verilog_bee ,

the PLL input should be connected to IBUFDS_GTE3/ODIV2. It cannot be connected to IBUFDS_GTE3/O.

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eschidl
Xilinx Employee
Xilinx Employee
528 Views
Registered: ‎10-19-2011

Hi @verilog_bee ,

the PLL input should be connected to IBUFDS_GTE3/ODIV2. It cannot be connected to IBUFDS_GTE3/O.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post