03-25-2021 05:41 PM - edited 03-25-2021 05:50 PM
We used the GTY transceiver in our design and are facing a problem that Phase alignment can not be done. The following is some detail.
[ Configuration of GTY]
We tried to change the TXOUTCLK source to "TXPLLREFCLK DIV1", the result is the same.
While TX buffer is Enabled in configuration, it would be bypassed when actually used.
Therefore we are expecting the phase alignment logic to work as described in Figure 3-19 in datasheet.
With our current design, phase alignment is done normally in simulation. However, in our board evaluation,
phase alignment can not be finished and we are struggling to find the cause.
As described in P142 of datasheet, we toggled TXDLYSRESET signal after
- Powering up of GTY TX
- Setting of TXRESETDONE signal
- Changing line rate to 9.8G
And we observed that TXDLYSRESETDONE signal toggled but TXPHALIGNDONE didn't.
And we also observed that the frequency of TXOUTCLK is correct. (245MHz according to equation 3-1)
While we are not sure whether it concerns, we find that the pulse width of TXRESETDONE signal is 80ns
instead of >=100ns described in P142 of datasheet.
What should we confirm next for debugging?
Your help is greatly appreciated.
03-26-2021 08:14 AM
You need to set the buffer in the GT wizard to bypass so that Vivado will hook up all the connections and all the attributes you need to use buffer bypass successfully. If you then have it make an example design you will be able to accomplish phase alignment by pulsing one command line. The wizard will set up everything for you. What you are doing is complicating something that should be very easy.