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ghasemi_r
Adventurer
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Registered: ‎05-07-2018

Phase alignment with rxslide in PMA mode (KC705)

Hi,

I use 7 series FPGAs Transceivers Wizard (3.6) for KC705 and after compensating slip, I have the right data communication between 2 boards. But I face some issues with RX recovered clock, the RX clock phase relies on the number of bit slip values. As you can see in the picture below. Even I reached this relative formula :

Recovered Clock Phase = (((64 -BIT SLIP))/64×360 ) - 180°

data width = 64 bit

I want to remove the phase difference between RX & TX clock, and from Xilinx documents, I understand if I set rx_slide_mode on PMA, I can reach my purpose. 

Is that right? 

How can I set rx_slide_mode through DRP address? Is there any other way?

If I enable Rx buffer, phase difference will go??

Thanks.

 

 

 

slip.png
17 Replies
roym
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Registered: ‎07-30-2007

If you use the RX buffer you should be able to use the TXOUTCLK to drive both the TXUSRCLKs and the RXUSRCLKs as long as the link is synchronous.  I think the link must be synchronous since you can see a stable phase relationship between the recovered clock and the TXOUTCLK. The RXSLIDE needs to be used to frame the serial to parallel conversion properly.  I don't think you should use it to match the clocks.




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behnam_2705new
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Registered: ‎03-16-2019

why the phase of the clock is important to you?

from my point of view having a stable phase difference is adequate. phase of the signal is related to the where you see the signal.

does two RX and Tx clock have the same path before you monitor them?

you can not even measure simply sinusoid signal with phase 0 and phase 90 by seeing the signal wherever you want,

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borisq
Xilinx Employee
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Registered: ‎08-07-2007

hi @ghasemi_r 

 

if you want the txusrclk/2 and rxusrclk/2 to be aligned in phase, you can just use a common bufg to drive both clocks.

Below is an example in a synchronous pcie system.

your clocking is synchronous so this applies to your design as well.

 

Below message is compied from UG476 page 297

 

If the channel is configured so the same oscillator drives the reference clock for the transmitter and the receiver, TXOUTCLK can be used to drive RXUSRCLK and RXUSRCLK2 in the same way that they are used to drive TXUSRCLK and TXUSRCLK2. When clock correction is turned off or the RX buffer is bypassed, RX phase alignment must be used to align the serial clock and the parallel clocks.

 

Thanks,

Boris

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sync_clocking.png
ghasemi_r
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Hi

I need to do Phase alignment between two KC705. By this work, I will have deterministic latency between 2 boards and most importantly, I need to transfer the same clock from Board1 to Board2 without any difference in Frequency and Phase (Especially on phase). I read UG476 page236 and it mentions, PMA as RXSLIDE_MODE does this function. It shifts Parallel data and changes the Phase, PCS mode shifts parallel data but does not change the Phase.

On the base of my first Message, there is a relation between the number of bit slip and Phase movement. 

I want to know, PMA mode will compensate for the Phase difference between recovered RXCLK Board2 and TXCLK Board1?

in the end, I must clarify I need to reach the same frequency and phase between 2 boards with distinct local CLOCK 

Thanks 

slip3.PNG
slip2.png
arashkm73
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Registered: ‎08-01-2017


I read UG476 page236 and it mentions, PMA as RXSLIDE_MODE does this function. It shifts Parallel data and changes the Phase, PCS mode shifts parallel data but does not change the Phase.

I want to know, PMA mode will compensate for the Phase difference between recovered RXCLK Board2 and TXCLK Board1?

 


I don't think the purpose of RXSLIDE_MODE is adjusting the phase of clocks. Could you mention your final purpose of adjusting the phase and frequency of clocks?

As your figure shows, your board 2's transmitter is synchronized with Board 1's transmitter and you have a synchronized communication. 

Why do you exactly need the clocks to be phase aligned?

ghasemi_r
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Registered: ‎05-07-2018

I need to have the same CLK in my process.
as @arashkm73 mentioned "I don't think the purpose of RXSLIDE_MODE is adjusting the phase of clocks", then what is the purpose of PMA rxslide_mode?

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behnam_2705new
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Registered: ‎03-16-2019

you can align your received data manually by enabling RX_SLIDE_MODE.

"RXSLIDE can be used to override the automatic comma alignment and to shift the parallel data "

you can set RXSLIDE_MODE, PCS or PMA, when you set this attribute to PCS your clock phase alignment haven't changed but if you select that to PMA your clock phase might be changed. it can affect the phase alignment procedure.

"The RX phase alignment circuit is used to adjust the phase difference between the SIPO parallel clock domain and the RX XCLK domain to effect reliable data transfer from the SIPO into the PCS. S. It also performs the RX delay alignment by adjusting the RXUSRCLK to compensate for the temperature and voltage variations. The combined RX phase and delay alignments can be automatically performed by the GTX/GTH transceiver or manually controlled by the user." 

Actually I can not find out why you need a similar clock phase in your transceiver application.

can you talk more about your project? 

 

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ghasemi_r
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Registered: ‎05-07-2018

Hello

I am very thankful because of the answers.

fixed and deterministic latency between boards are my main purpose when I used symmetrical fiber optics. I send a trigger from one board to others and it is very critical for me to receive that concurrently, in specific and synchronous time.  

Thanks

 

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behnam_2705new
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Registered: ‎03-16-2019

you will not achieve concurrently when you want to connect to board with each other. determining the exact time latency is an undetermined procedure. latency will change when your fiber optics changes(1m to 10km length). actually your clock generator may have some differences in their clock output(some ppm) and you can not make a clock loop. you must have one source and the other recovered your clock. not both of them recovering clock by their receiving data.

does symmetrical fiber mean equally fast upload and download speeds?

what protocol do you use for transmitting data? 

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borisq
Xilinx Employee
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Registered: ‎08-07-2007

hi @ghasemi_r 

 

i'm afraid the phase is not determined between 'recovered local clk1' and 'local clock1'.

it seems you want to use recovered clock to be the trasnmiter clock on Board #2.

if so, you may want to look at this PICXO solution. By this solution, the frequency of TXCLK board 2 is the same as TXCLK board 1, but phase is not guaranteed.

https://www.xilinx.com/support/documentation/application_notes/xapp589-VCXO.pdf

 

Thanks,

Boris

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behnam_2705new
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Hi @borisq 

Thanks for your useful document, I haven't seen it before. this is so helpful for me and the others who want to work in serial transceiver field.

but I cannot download the reference design because of 

"We cannot fulfill your request as your account has failed export compliance verification."

could you help me to download this helpful reference design? I can send to you or other Xilinx employee my information.

 

 

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ghasemi_r
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Hi @borisq 

you mentioned: "I'm afraid the phase is not determined between 'recovered local clk1' and 'local clock1'." 

then you are certain that PMA rxslide Mode can not adjust the phase of recovered RXCLOCK(Board2) with  TXCLOCK(Board1). TRUE?

control of PPM factor for ClOCK will be helpful? 

Thanks for your perfect information.

 

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behnam_2705new
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this is based on your application, you should declare your protocol or the way that you have selected for transmitting data.

in some way, the procedure must have the exact clock of the transceiver but the others can tolerate some PPMs by inserting some bits as stuff (bit stuffing). this is based on your procedure or algorithm behind your transmission data.

if you want to insert bit stuff, you should find out the difference PPM that your transceiver and receiver clock have than insert or delete some bits. 

 

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ghasemi_r
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Hi
I know about PPM, I want to know the reduction of PPM factor helps me to reach the phase of TX on RX side?
Thanks
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behnam_2705new
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I don't think so,PPM is used to give a relative measure of the frequency difference of two oscillators.

behnam_2705new
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do you find your answer?
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ghasemi_r
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Hi,

Thanks for asking

I find a solution to my issue. 

:)

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