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Observer
Observer
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Registered: ‎06-13-2018

Placement errors in JESD PHy pin assignments

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Hi

I am working on Kintex-7 Ultrascale and in my project, I have 3 high speed ADCs and DACs. SERDES lines of these three ADCs and DACs are shared between two GTH Quad. ADC1, DAC2 and DAC3 are sharing same GTH Quad and ADC2, ADC3, and DAC1 are sharing another GTH Quad. I am using block design for this project and in that there are JESD RX, JESD TX and JESD PHY IPs. ADC1 JESD and DAC2 JESD and DAC3 JESD are connected to single JESD PHY. Same way for other remaining devices.

I am getting placement errors while doing implementation process.

Can anyone help me on this?

Thanks in advance.

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Xilinx Employee
Xilinx Employee
196 Views
Registered: ‎03-30-2016

Re: Placement errors in JESD PHy pin assignments

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Hello @cpandya 

Your current pin-assignment usecase is not implementable. Please see also pictures from my previous post.

>Regarding your second question, I modified a block design and put ADC-1 JESD and DAC-3 JESD with single JESD_PHY, I am still getting critical warnings and it ends up with wrong pin assignment for one of ADC-1 serdes line.

I just checked above pin assignment using xcku085-flva1517. Something like this .. ...

ADC-1 use R4 : QUAD229 RX CH1
ADC-1 use T2 : QUAD229 RX CH0
DAC-3 use T6 : QUAD229 TX CH1
DAC-3 use N8 : QUAD229 TX CH3

ADC-3 use W38 : QUAD127 RX CH2
ADC-3 use V36 : QUAD127 RX CH3
DAC-1 use AA34 : QUAD127 TX CH1
DAC-1 use W34 : QUAD127 TX CH3

If you want to merge JESD_PHY IP into a single instance, those red-marked pin should be assigned on the same GTH channel.

As an experiment , please try one single JESD_PHY IP with the following pin assignment to understand the pin-assignment rule.
   ADC-1 use R4 : QUAD229 RX CH1
   ADC-1 use T2 : QUAD229 RX CH0
   DAC-3 use T6 : QUAD229 TX CH1
   DAC-3 use U4 : QUAD229 TX CH0

Regards
Leo

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Adventurer
Adventurer
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Registered: ‎12-27-2018

Re: Placement errors in JESD PHy pin assignments

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Hi @cpandya


JESD implementation problem , will most likely caused by either
1. pin assignment issue
2. JESD IP and PHY connectivity issue.
 
Perhaps if you willing sharing a simple diagram of your design on JESD IP and JESD PHY connection.  and implementation error messages you see during implementation,
some people can give you a quick hints.
 
Best regards.
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Observer
Observer
262 Views
Registered: ‎06-13-2018

Re: Placement errors in JESD PHy pin assignments

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Thanks @yuko.2828  for replying,

I have also attached snapshot of ADC and DAC JESD modules
DACDACADCADC
Here is more details,

ADC-1 serdes lines connected to Quad_1, DAC-1 sedes lines are connected to Quad_2, ADC-2 serdes lines are connected to Quad_3, DAC-2 sedes lines are connected to Quad_4, ADC-3 serdes lines are connected to Quad_2 and  DAC-3 sedes lines are connected to Quad_1.Reference clock-1 is only connected to Quad_1 and another reference clock-2 is connected to Quad_2.


Right now, I am using one same jesd_rx and jesd_phy_rx IP for all three ADCs and one same jesd_tx and jesd_phy_tx for all three DACs. I am using "Include shared logic in example design" for both jesd_rx and jesd_tx IPs and "Include shared logic in core" for both jesd_phy_rx and jesd_phy_tx IPs.

When I add only two ADCs and DACs, I am able to generate bin file with given below critical warnings.
[Vivado 12-2285] Cannot set LOC property of instance 'dac2/jesd_tx/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_txx2_phy_gt_i/inst/gen_gtwizard_gthe3_top.jesd204_txx2_phy_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST'... Instance dac2/jesd_tx/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_txx2_phy_gt_i/inst/gen_gtwizard_gthe3_top.jesd204_txx2_phy_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST can not be placed in GTHE3_CHANNEL of site GTHE3_CHANNEL_X0Y8 because the bel is occupied by dac1/jesd_tx/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_txx2_phy_gt_i/inst/gen_gtwizard_gthe3_top.jesd204_txx2_phy_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST. This could be caused by bel constraint conflict ["./jesd/jesd204_txx2_phy/ip_0/synth/jesd204_txx2_phy_gt.xdc":57]

[Vivado 12-2285] Cannot set LOC property of instance 'dac2/jesd_tx/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_txx2_phy_gt_i/inst/gen_gtwizard_gthe3_top.jesd204_txx2_phy_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST'... Instance dac2/jesd_tx/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_txx2_phy_gt_i/inst/gen_gtwizard_gthe3_top.jesd204_txx2_phy_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST can not be placed in GTHE3_CHANNEL of site GTHE3_CHANNEL_X0Y9 because the bel is occupied by dac1/jesd_tx/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_txx2_phy_gt_i/inst/gen_gtwizard_gthe3_top.jesd204_txx2_phy_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST. This could be caused by bel constraint conflict ["./jesd/jesd204_txx2_phy/ip_0/synth/jesd204_txx2_phy_gt.xdc":70]

[Vivado 12-2285] Cannot set LOC property of instance 'adc1/jesd_rx/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_rxx2_phy_gt_i/inst/gen_gtwizard_gthe3_top.jesd204_rxx2_phy_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST'... Instance adc1/jesd_rx/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_rxx2_phy_gt_i/inst/gen_gtwizard_gthe3_top.jesd204_rxx2_phy_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST can not be placed in GTHE3_CHANNEL of site GTHE3_CHANNEL_X0Y8 because the bel is occupied by dac1/jesd_tx/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_txx2_phy_gt_i/inst/gen_gtwizard_gthe3_top.jesd204_txx2_phy_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST. This could be caused by bel constraint conflict ["./jesd/jesd204_rxx2_phy/ip_0/synth/jesd204_rxx2_phy_gt.xdc":57]

[Vivado 12-2285] Cannot set LOC property of instance 'adc1/jesd_rx/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_rxx2_phy_gt_i/inst/gen_gtwizard_gthe3_top.jesd204_rxx2_phy_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST'... Instance adc1/jesd_rx/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_rxx2_phy_gt_i/inst/gen_gtwizard_gthe3_top.jesd204_rxx2_phy_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST can not be placed in GTHE3_CHANNEL of site GTHE3_CHANNEL_X0Y9 because the bel is occupied by dac1/jesd_tx/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_txx2_phy_gt_i/inst/gen_gtwizard_gthe3_top.jesd204_txx2_phy_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST. This could be caused by bel constraint conflict ["./jesd/jesd204_rxx2_phy/ip_0/synth/jesd204_rxx2_phy_gt.xdc":70]

[Vivado 12-2285] Cannot set LOC property of instance 'adc2/jesd_rx/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_rxx2_phy_gt_i/inst/gen_gtwizard_gthe3_top.jesd204_rxx2_phy_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST'... Instance adc2/jesd_rx/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_rxx2_phy_gt_i/inst/gen_gtwizard_gthe3_top.jesd204_rxx2_phy_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST can not be placed in GTHE3_CHANNEL of site GTHE3_CHANNEL_X0Y8 because the bel is occupied by dac1/jesd_tx/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_txx2_phy_gt_i/inst/gen_gtwizard_gthe3_top.jesd204_txx2_phy_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST. This could be caused by bel constraint conflict ["./jesd/jesd204_rxx2_phy/ip_0/synth/jesd204_rxx2_phy_gt.xdc":57]

[Vivado 12-2285] Cannot set LOC property of instance 'adc2/jesd_rx/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_rxx2_phy_gt_i/inst/gen_gtwizard_gthe3_top.jesd204_rxx2_phy_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST'... Instance adc2/jesd_rx/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_rxx2_phy_gt_i/inst/gen_gtwizard_gthe3_top.jesd204_rxx2_phy_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST can not be placed in GTHE3_CHANNEL of site GTHE3_CHANNEL_X0Y9 because the bel is occupied by dac1/jesd_tx/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_txx2_phy_gt_i/inst/gen_gtwizard_gthe3_top.jesd204_txx2_phy_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST. This could be caused by bel constraint conflict ["./jesd/jesd204_rxx2_phy/ip_0/synth/jesd204_rxx2_phy_gt.xdc":70]

 

 

When I am trying to add third ADC and DAC, I am getting placement errors [Place 30-1161] Could not place all instances for rule!

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Xilinx Employee
Xilinx Employee
255 Views
Registered: ‎03-30-2016

Re: Placement errors in JESD PHy pin assignments

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Hello @cpandya 
# I am not so clear with your usecase. I don't know your device model, and I do not know your pin-assignment.
   But I do agree with @yuko.2828  that this is pin assignment issue.

1.  Why do you split JESD204_PHY for DAC (TX only) and ADC (RX only) ? Are you implementing DAC/ADC on different GTH quads ?
     # You can use JESD204_PHY TX & RX with different line-rate configuration (using different PLL)
        See also PG198 for example of JESD204_PHY and JESD204 IP connectivity.
        PG198.png

2. Are you trying to assigned DAC output (GTH TX output pins) to the same channel with ADC input (GTH RX input pins) ?
    #  If this is the case you will get this error during implementation.
        You cannot assign DAC TX on the same GTH quad of DAC RX , because it already occupied. ( see picture below)

        DAC_ADC_unused_pins.png

Hope this helps.

Regards
Leo

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Observer
Observer
215 Views
Registered: ‎06-13-2018

Re: Placement errors in JESD PHy pin assignments

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Thanks @karnanl,

I am using xcku085flva1517 package.
I wanted to combine ADC-1 and DAC-1 into one mod, so that they can be synchronized, but they are in different quads with separate gth clock.
In my case, ADC-1 and DAC-3 are in same GTH_229, DAC-1 and ADC-3 are in same GTH_127. DAC-2 is connected to GTH_230 and ADC-2 is connected to GTH_128. One clock is connected to GTH_229 and second clock is connected to GTH_127. I am using two serdes lines for each ADC and DAC.

ADC-1 has R4 and T2, DAC-3 has T6 and N8 serdes lines connections in GTH_229. Same way for ADC-3 has W38 and V36, DAC-1 has AA34 and W34 serdes lines in GTH_127.

Regarding your second question, I modified a block design and put ADC-1 JESD and DAC-3 JESD with single JESD_PHY, I am still getting critical warnings and it ends up with wrong pin assignment for one of ADC-1 serdes line.

It is either I am getting placement errors or wrong pin assignment with critical warning. How should I modify my design to get working?

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: Placement errors in JESD PHy pin assignments

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Hello @cpandya 

Your current pin-assignment usecase is not implementable. Please see also pictures from my previous post.

>Regarding your second question, I modified a block design and put ADC-1 JESD and DAC-3 JESD with single JESD_PHY, I am still getting critical warnings and it ends up with wrong pin assignment for one of ADC-1 serdes line.

I just checked above pin assignment using xcku085-flva1517. Something like this .. ...

ADC-1 use R4 : QUAD229 RX CH1
ADC-1 use T2 : QUAD229 RX CH0
DAC-3 use T6 : QUAD229 TX CH1
DAC-3 use N8 : QUAD229 TX CH3

ADC-3 use W38 : QUAD127 RX CH2
ADC-3 use V36 : QUAD127 RX CH3
DAC-1 use AA34 : QUAD127 TX CH1
DAC-1 use W34 : QUAD127 TX CH3

If you want to merge JESD_PHY IP into a single instance, those red-marked pin should be assigned on the same GTH channel.

As an experiment , please try one single JESD_PHY IP with the following pin assignment to understand the pin-assignment rule.
   ADC-1 use R4 : QUAD229 RX CH1
   ADC-1 use T2 : QUAD229 RX CH0
   DAC-3 use T6 : QUAD229 TX CH1
   DAC-3 use U4 : QUAD229 TX CH0

Regards
Leo

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Observer
Observer
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Registered: ‎06-13-2018

Re: Placement errors in JESD PHy pin assignments

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Thanks @karnanl and @yuko.2828 for helping here.

Above suggestion are working for me.