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Explorer
Explorer
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Registered: ‎01-15-2008

Problem with IBUFDS_GTE4 on VCU128

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Hello all,

I am working on a VCU128 design employing the GTY transceivers, and I'm stuck at a very basic thing: the IBUFDS_GTE4 seems not to be working.

To see the very basic functionality of the buffer, I've implemented a toggle FF driven by the ref_clk, via IBUFDS_GTE4 and a BUF_GT.  Here's the HDL:

wire gty_refclk;
wire gty_refclk_int;
IBUFDS_GTE4 #(
.REFCLK_EN_TX_PATH(1'b0), // Refer to Transceiver User Guide
.REFCLK_HROW_CK_SEL(2'b00), // Refer to Transceiver User Guide
.REFCLK_ICNTL_RX(2'b00) // Refer to Transceiver User Guide
)
IBUFDS_GTE4_0 (
.O(gty_refclk), // 1-bit output: Refer to Transceiver User Guide
.ODIV2(gty_refclk_int), // 1-bit output: Refer to Transceiver User Guide
.CEB(1'b0), // 1-bit input: Refer to Transceiver User Guide
.I(refclk_p), // 1-bit input: Refer to Transceiver User Guide
.IB(refclk_n) // 1-bit input: Refer to Transceiver User Guide
);

wire gty_refclk_int_buf;
BUFG_GT BUFG_GT_REFCLK (
.O(gty_refclk_int_buf), // 1-bit output: Buffer
.CE(1'b1), // 1-bit input: Buffer enable
.CEMASK(1'b0), // 1-bit input: CE Mask
.CLR(1'b0), // 1-bit input: Asynchronous clear
.CLRMASK(1'b0), // 1-bit input: CLR Mask
.DIV(3'b000), // 3-bit input: Dynamic divide Value
.I(gty_refclk_int) // 1-bit input: Buffer
);

reg testflop = 0;
always @(posedge gty_refclk_int_buf) testflop <= !testflop;
assign test_out = testflop;

And here is the implemented design:

capture.jpg

The input is about 800mvpp differential at 500MHz; on the VCU128 this pair is ac-coupled into AN40/AN41.  Probing the coupling caps I can see the signal, and I can also see the 900mv bias voltage (MGTAVCC) on the FPGA side of those caps.  But test_out is not toggling.

In simulation, the proper 250MHz output is produced.  I've tried a lower frequency in case there were signal integrity problems with my source (though the differential signal looks fine).

The only mystery about the implementation is about the value for REFCLK_INCTL_RX (= 00).  UG578 says to "use the recommended value from the WIzard", but I don't see any Wizard which generates code for the IBUFDS_GTE4 (my Wizard-generated GTY core resulted in a single-ended refclk input; I had to put the IBUFDS_GTE4 in myself).

One input, one output, one filp-flop; doesn't work.  What am I doing wrong?

 

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Explorer
Explorer
373 Views
Registered: ‎01-15-2008

Thanks for your help, the problem was in my understanding of the "Vitis" tool, which was new to me.  In fact my bitfile had never been updated, so I was programming the FPGA with the old design which didn't have the BUFG_GT or toggle FF at all.

The design has a MicroBlaze processor, to set up a few peripherals needed to generate the off-board clock.  In SDK, I was used to "exporting the hardware with bitstream" and then recompiling.  In Vitis it seems you need to also do a "clean all" to get the new bitfile in there.

Now my 500MHz refclk does produce the 250MHz at the testpoint.

 

Thanks again

 

Rick

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @rikraf ,

I do not see an immediate error in your setup. To get the IBUFDS_GTE example generate the example design of the core you created. It should then be placed in the toplevel there.

How do you observe the FF? external on a pin or with ILA? You could also implement a counter on the clock and observe the counter value in the ILA. ILA would only rely on internal signals. You could run the ILA on a system clock of the board. It would not need to be cycle true here.

Maybe try another quad, like 131, where you have an onboard clock coming in.

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Highlighted
Explorer
Explorer
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Registered: ‎01-15-2008

Thanks for the reply.  I observe the test_out signal on an external pin.  I can try with ILA, too.

When I generated the example design it also had a single-ended refclk input.  I will try that again, maybe I misuderstood something.

Am I correct in setting both CEMASK and CLRMASK to 0 on the BUFG_GT?  

I'll try the onboard clock, good idea.

Rick

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Xilinx Employee
Xilinx Employee
400 Views
Registered: ‎10-19-2011

Hi @rikraf ,

just reduce the BUFG_GT instantiation to this:

BUFG_GT BUFG_GT_REFCLK (
.O(gty_refclk_int_buf), // 1-bit output: Buffer
.I(gty_refclk_int) // 1-bit input: Buffer
);

The SW will do the rest.

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Highlighted
Explorer
Explorer
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Registered: ‎01-15-2008

Thanks for your help, the problem was in my understanding of the "Vitis" tool, which was new to me.  In fact my bitfile had never been updated, so I was programming the FPGA with the old design which didn't have the BUFG_GT or toggle FF at all.

The design has a MicroBlaze processor, to set up a few peripherals needed to generate the off-board clock.  In SDK, I was used to "exporting the hardware with bitstream" and then recompiling.  In Vitis it seems you need to also do a "clean all" to get the new bitfile in there.

Now my 500MHz refclk does produce the 250MHz at the testpoint.

 

Thanks again

 

Rick

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