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Visitor trafalgar
Registered: ‎01-24-2019

Problems of zcu102 GTH transceiver on board achievement

  Hello, I am designing a protocol like Aurora 64/66B,so I have to use transceiver to test my design. Now I get two zcu102 boards and choose "UltraScale FPGAs Transceivers Wizard" ip to use GTH.

  First, I learn the example design on how to drive this ip in simulation and the simulation is successful, the data from my protocol successfully transfer to another protocol.     The data flow is shown as below:

  my portocol1 ----  GTH1  ---- GTH2 ---- my protocol2.

  After simulation, I want to implement on board to test problems like bit error rate,DC balance and CID but fail. 

  It seems that the transceiver is always on the status of “reset” because the ip signals “gtwiz_userclk_tx_reset_in” and “gtwiz_userclk_tx_reset_in” are always high. This two signals are driven by “rxpmaresetdone_out” and "txpmaresetdone_out" and I copy the example design codes as below:


  assign hb0_gtwiz_userclk_tx_reset_int = ~(&txpmaresetdone_int);

  assign hb0_gtwiz_userclk_rx_reset_int = ~(&rxpmaresetdone_int);



  Actually,the "rxpmaresetdone_out" and "txpmaresetdone_out" are always the value "2'b00",so the tx and rx are always on the status of "reset".

  I suspect the problem occurs on these two clock "gtwiz_reset_clk_freerun_in" and "gtrefclk00_in". These two clocks don't drive the transceiver effectively.

  The "gtwiz_reset_clk_freerun_in"s source is zcu102 "USER_SI570". USER_SI570's frequency is 300Mhz, so i use the ip"clocking wizard" to get the 250Mhz "gtwiz_reset_clk_freerun_in".

  The "gtrefclk00_in" is copied from the example design. It's source is "USER_MGT_SI570(clock 1)". It's actually the reference clock0 of Quad 129.

  I have tried both my design and the example design, the GTH transceiver is always on reset. Of course, I have given all the constraints and tried several times but fail. I can't figure out where the problem is but I suspect the problem occur on the two clocks. The phenomenon of simulation if I don't give these two clock and implementation is the same. So I guess these two clocks don‘t drive the ip actually.

  The configuration of the ip is shown as below:


To implement the example design, I add the addtional clock and constraints but fails as my design.

  clk_wiz_0 clk_wiz_1



set_property package_pin L28 [get_ports mgtrefclk0_x0y2_n]
set_property package_pin L27 [get_ports mgtrefclk0_x0y2_p]
set_property package_pin AL8 [get_ports clk_in1_p]
set_property package_pin AL7 [get_ports clk_in1_n]
set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_in1_p]
set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_in1_n]
create_clock -name clk_mgtrefclk0_x0y2_p -period 16.0 [get_ports mgtrefclk0_x0y2_p]

# False path constraints
# ----------------------------------------------------------------------------------------------------------------------
set_false_path -to [get_cells -hierarchical -filter {NAME =~ *bit_synchronizer*inst/i_in_meta_reg}]
##set_false_path -to [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_*_reg}]
set_false_path -to [get_pins -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_meta_reg/D}]
set_false_path -to [get_pins -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_meta_reg/PRE}]
set_false_path -to [get_pins -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_sync1_reg/PRE}]
set_false_path -to [get_pins -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_sync2_reg/PRE}]
set_false_path -to [get_pins -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_sync3_reg/PRE}]
set_false_path -to [get_pins -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_out_reg/PRE}]

set_property PACKAGE_PIN AG15 [get_ports hb_gtwiz_reset_all_in]
set_property IOSTANDARD LVCMOS33 [get_ports hb_gtwiz_reset_all_in]


  I only want to  know how to run or drive GTH transceiver on zcu102.

  Thanks you.

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1 Reply
Visitor trafalgar
Registered: ‎01-24-2019

回复: Problems of zcu102 GTH transceiver on board achievement

files is the top level code.

Constraints are below:

set_property PACKAGE_PIN AG13 [get_ports sw]
set_property PACKAGE_PIN AL12 [get_ports {LEDS[7]}]
set_property PACKAGE_PIN AH14 [get_ports {LEDS[6]}]
set_property PACKAGE_PIN AH13 [get_ports {LEDS[5]}]
set_property PACKAGE_PIN AJ15 [get_ports {LEDS[4]}]
set_property PACKAGE_PIN AJ14 [get_ports {LEDS[3]}]
set_property PACKAGE_PIN AE13 [get_ports {LEDS[2]}]
set_property PACKAGE_PIN AF13 [get_ports {LEDS[1]}]
set_property PACKAGE_PIN AG14 [get_ports {LEDS[0]}]

set_property IOSTANDARD LVCMOS33 [get_ports sw]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[0]}]

set_property PACKAGE_PIN AG15 [get_ports reset]
set_property IOSTANDARD LVCMOS33 [get_ports reset]

set_property PACKAGE_PIN L28 [get_ports clk_in1_n1]
set_property PACKAGE_PIN L27 [get_ports clk_in1_p1]

create_clock -name clk_mgtrefclk0_x0y2_p -period 16.0 [get_ports clk_in1_p1]
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