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Problems with aurora 64/66 core on Virtex 6

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Visitor
Posts: 12
Registered: ‎10-10-2017

Problems with aurora 64/66 core on Virtex 6

Hello.

I try to implement aurora 64/66 core of version 7.3.

FPGA is xc6vsx475t ff1759 -2.

The development environment is ISE 14.7 x64.

I tried to implement an interface between another FPGA and this. I found out, that on the other side signals "lane_up" are all true, but in virtex 6 they are 0. So, if "lane_up" are 0, then the core can't end reset. Why could it be?

I tried to implement example design of the core. ILA shows strange values, like "lane_up" and "channel_up" both are equal to 1, even when there is no interface on the other side and the LED that must show the same value does not light up. I have problems with setup time too, but this is strange, because in ucf file I changed only LOCs and have commented some ports in top module, because I have no buttons for reset.

The frequency of init_clk is 100 MHz.

Modified ucf and top level and core settings are in attachment.

Posts: 2,521
Kudos: 303
Solutions: 228
Registered: ‎02-16-2010

Re: Problems with aurora 64/66 core on Virtex 6

If you do not have buttons to apply reset, can you use VIO core to apply them? To ensure proper link up of the IP, you will need to apply the reset and pma_init inputs during startup of the design.

Please report your observations after applying the RESET and PMA_INIT inputs to the core using VIO.
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Visitor
Posts: 12
Registered: ‎10-10-2017

Re: Problems with aurora 64/66 core on Virtex 6

I have added a simple process, that acts like the testbench processes:

 

	do_reset <= async_out_i(0);
	
	rst_proc:process(user_clk_i)
	begin
		if rising_edge(user_clk_i) then
			if do_reset='1' then
				rst_counter <= 0;
			else
				if rst_counter<16 then
					rst_counter <= rst_counter + 1;
				end if;
			end if;
			if rst_counter<5 then
				RESET <= '1';
			else
				RESET <= '0';
			end if;
			if rst_counter<16 then
				PMA_INIT <= '1';
			else
				PMA_INIT <= '0';
			end if;
		end if;
	end process;

 

In chipscope I have set async_out_i as a pushbutton (high).

Before these actions all signals in VIO were 0, and 3 of 4 signals "lane_up" were shown with bidirectional arrow. But, when I had changed the special inner reset signal as 1, the arrows disappeared.

Now signal values are the same, but when I set that inner reset, arrows remain.

Changing async_out_i(0) does not cause any changes.

And before the changes I saw strange values in ILA, but now, when I try to do "trigger immidiate", chipscope says, that there is some problems with clock on ILA, and does not show data.

Posts: 2,521
Kudos: 303
Solutions: 228
Registered: ‎02-16-2010

Re: Problems with aurora 64/66 core on Virtex 6

What is the device interfacing with Virtex-6?
Which version of the IP used on the other device?

Can you try to test the design by setting loopback port at the IP interface to "010"?

With your reset sequence, your are asserting reset before pma_init. This is good. But release the reset after PMA_INIT is released and when user_clk is stable.
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Visitor
Posts: 12
Registered: ‎10-10-2017

Re: Problems with aurora 64/66 core on Virtex 6

[ Edited ]

I use virtex 7 with core version 11.2.
I thought, that signals "lane_up" can be 1 even if there is no device on the other side. But perhaps I am not right.
I tried to change loopback mode, and when the mode is 010 or 001, channel_up=1.
When loopback=100, channel_up=1 most of the time, but often changes to 0 for a small period.
When loopback=110, channel_up=0.
I think, that the problem is that I use different versions of IP. In user guide is written, that there are compability parameters in the verilog file generated by core, but I cannot find them in that file. So, is there any way to turn on compability without them, or to change a version of IP in vivado? Or should I change the entire development environment version to change IP?

Posts: 2,521
Kudos: 303
Solutions: 228
Registered: ‎02-16-2010

Re: Problems with aurora 64/66 core on Virtex 6

You can only test "010" and "001" loopback modes with single board test.

Regarding compatibility parameters, are you referring to BACKWARD_COMP_MODE1, BACKWARD_COMP_MODE2, and BACKWARD_COMP_MODE3?

Can you please share <user_component_name>_core.v of your virtex-7 IP? I would like to see if the attributes are missing in this file.
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Visitor
Posts: 12
Registered: ‎10-10-2017

Re: Problems with aurora 64/66 core on Virtex 6

1) I have two boards, one with virtex 6 and other with virtex 7.

 

2) Yes, I speak about them.

 

3) Here it is:

Posts: 2,521
Kudos: 303
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Registered: ‎02-16-2010

Re: Problems with aurora 64/66 core on Virtex 6

In the file you attached, I find the backward compatibility parameters on line 400,401,402.

localparam BACKWARD_COMP_MODE1 = 1'b0; //disable check for interCB gap
localparam BACKWARD_COMP_MODE2 = 1'b0; //reduce RXCDR lock time, Block Sync SH max count, disable CDR FSM in wrapper
localparam BACKWARD_COMP_MODE3 = 1'b0; //clear hot-plug counter with any valid btf detected
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Visitor
Posts: 12
Registered: ‎10-10-2017

Re: Problems with aurora 64/66 core on Virtex 6

I have tried to change the parameters, but it still does not work. I think, that it could be a hardware problem. I will speak with the manufacturer of the plate about it. Thank you for help.

Posts: 2,521
Kudos: 303
Solutions: 228
Registered: ‎02-16-2010

Re: Problems with aurora 64/66 core on Virtex 6

Can you try using IBERT to confirm about any hardware problem?
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