01-12-2018 08:45 AM
I try to implement aurora 64/66 core of version 7.3.
FPGA is xc6vsx475t ff1759 -2.
The development environment is ISE 14.7 x64.
I tried to implement an interface between another FPGA and this. I found out, that on the other side signals "lane_up" are all true, but in virtex 6 they are 0. So, if "lane_up" are 0, then the core can't end reset. Why could it be?
I tried to implement example design of the core. ILA shows strange values, like "lane_up" and "channel_up" both are equal to 1, even when there is no interface on the other side and the LED that must show the same value does not light up. I have problems with setup time too, but this is strange, because in ucf file I changed only LOCs and have commented some ports in top module, because I have no buttons for reset.
The frequency of init_clk is 100 MHz.
Modified ucf and top level and core settings are in attachment.
01-12-2018 11:08 AM
01-15-2018 03:45 AM
I have added a simple process, that acts like the testbench processes:
do_reset <= async_out_i(0); rst_proc:process(user_clk_i) begin if rising_edge(user_clk_i) then if do_reset='1' then rst_counter <= 0; else if rst_counter<16 then rst_counter <= rst_counter + 1; end if; end if; if rst_counter<5 then RESET <= '1'; else RESET <= '0'; end if; if rst_counter<16 then PMA_INIT <= '1'; else PMA_INIT <= '0'; end if; end if; end process;
In chipscope I have set async_out_i as a pushbutton (high).
Before these actions all signals in VIO were 0, and 3 of 4 signals "lane_up" were shown with bidirectional arrow. But, when I had changed the special inner reset signal as 1, the arrows disappeared.
Now signal values are the same, but when I set that inner reset, arrows remain.
Changing async_out_i(0) does not cause any changes.
And before the changes I saw strange values in ILA, but now, when I try to do "trigger immidiate", chipscope says, that there is some problems with clock on ILA, and does not show data.
01-19-2018 01:06 PM
01-23-2018 06:08 AM - edited 01-23-2018 06:10 AM
I use virtex 7 with core version 11.2.
I thought, that signals "lane_up" can be 1 even if there is no device on the other side. But perhaps I am not right.
I tried to change loopback mode, and when the mode is 010 or 001, channel_up=1.
When loopback=100, channel_up=1 most of the time, but often changes to 0 for a small period.
When loopback=110, channel_up=0.
I think, that the problem is that I use different versions of IP. In user guide is written, that there are compability parameters in the verilog file generated by core, but I cannot find them in that file. So, is there any way to turn on compability without them, or to change a version of IP in vivado? Or should I change the entire development environment version to change IP?
01-23-2018 08:28 AM
01-24-2018 08:21 AM
02-05-2018 08:39 AM
I have tried to change the parameters, but it still does not work. I think, that it could be a hardware problem. I will speak with the manufacturer of the plate about it. Thank you for help.
02-05-2018 08:59 AM