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Visitor
Visitor
1,806 Views
Registered: ‎05-10-2019

Python interfacing for IBERT design

I am using the AVNET board. FPGA is programmed with IBERT design. But I need to save the data for a long time. Is there any python script interface with vivado processor? If so, please suggest me an idea.

32 Replies
Xilinx Employee
Xilinx Employee
1,720 Views
Registered: ‎10-19-2011

Hi @vilashini ,

there is no direct interface for Python to Vivado so that you could run Vivado commands directly in Python.
Vivado is controlled through a Tcl interface.
All Vivado user commands are given as Tcl commands. So the input for scripting would be the Vivado Tcl console or the Vivado Tcl shell.

What you could do is to call the Vivado Tcl shell from Python in batch mode, but it is still Tcl running underneath.

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Visitor
Visitor
1,702 Views
Registered: ‎05-10-2019

proc write_xadc {i} {

        set systemTime [clock seconds]

        puts -nonewline [clock format $systemTime -format %H:%M:%S]

    puts "  $i"

    flush stdout

}

 

proc do {end_time} {

    set end 0

    while {$end < $end_time} {

        after 1000

               write_xadc [get_property RX_BER [get_hw_sio_links]]

        incr end

    }

}

 

do 10

 

I have used the above coding. Data is printing in the Tcl console. But, I want to log the data in the .txt or .csv file. Can you please suggest to me?

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Xilinx Employee
Xilinx Employee
1,692 Views
Registered: ‎10-19-2011

hi @vilashini ,

the 'puts' command allows a file descriptor to print to. Please check with the standard Tcl documentation.

You need to open a file for writing first.

e.g.

set fileid [open <./blah> w]
puts $fileid "some text"

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Visitor
Visitor
1,679 Views
Registered: ‎05-10-2019

proc write_xadc {i} {

        set systemTime [clock seconds]

        set fp [open “myfile.txt” w+]

        puts -nonewline [clock format $systemTime -format %H:%M:%S]      

        puts $fp “$i”

        close $fp

    flush stdout

}

 

The file is opening in the folder. But, I need to print the timestamp and data into the file continuously. How will I do?

 

proc do {end_time} {

    set end 0

    while {$end < $end_time} {

        after 1000

               write_xadc [get_property RX_BER [get_hw_sio_links]]

        incr end

    }

}

do 10

 

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Visitor
Visitor
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Registered: ‎05-10-2019

set systemTime [clock seconds]

        set fp [open “myfile.txt” w+]

        puts $fp “[clock format $systemTime -format %H:%M:%S]”   

        puts $fp “ $i”

       close $fp

This command is printing into the file only once. How will i log the data continuously?

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Xilinx Employee
Xilinx Employee
1,666 Views
Registered: ‎10-19-2011

hi @vilashini ,

open the file before the 'while' and close it after.
Give the file ID as an additional parameter to the procedure write_xadc.

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Visitor
Visitor
1,647 Views
Registered: ‎05-10-2019

proc write_xadc {i,fp} {

        set systemTime [clock seconds]

        puts $fp “[clock format $systemTime -format %H:%M:%S]”   

 

        puts $fp “ $i”

    flush stdout

 

}

 

proc do {end_time} {

    set end 0

        set fp [open “myfile.txt” w+]

    while {$end < $end_time} {

        after 1000

               write_xadc [get_property RX_BER [get_hw_sio_links], get_property myfile [get_files]]

        incr end

    }

       close $fp

}

do 10

 

I am getting an error showing "Too many positional options when parsing"

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Visitor
Visitor
1,646 Views
Registered: ‎05-10-2019

Please suggest me the commands for passing the file name, since I am new to vivado.

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Visitor
Visitor
1,639 Views
Registered: ‎05-10-2019

proc write_xadc {end_time} {

        set filename C:/Users/Vilashini/Desktop/XADC_dump.csv

        set fileId [open $filename "w"]

        set end 0

    while {$end < $end_time} {

               after 1000

               set systemTime [clock seconds]

               puts -nonewline $fileId [clock format $systemTime -format %H:%M:%S]

               puts -nonewline $fileId ","

 

               puts -nonewline $fileId [get_property RX_BER [get_hw_sio_links]]

               puts -nonewline $fileId " "

               flush stdout

        incr end

    }

        close $fileId

}

 

If I execute this above program, the file is not been created and also values have not been logged into the file.

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Visitor
Visitor
1,639 Views
Registered: ‎05-10-2019

proc write_xadc {end_time} {

        set filename C:/Users/Moorthi/Desktop/XADC_dump.csv

        set fileId [open $filename “w”]

        set end 0

        while {$end < $end_time} {

               after 1000

               set systemTime [clock seconds]

               puts -nonewline $fileId [clock format $systemTime -format %H:%M:%S]

               puts -nonewline $fileId ","

 

               puts -nonewline $fileId [get_property RX_BER [get_hw_sio_links]]

               puts $fileId " "

               flush stdout

        incr end

    }

        close $fileId

}

write_xadc 10

 

I have executed this program. Successfully loaded the values into the file. But if I run the loop 10 times, the same value is loading. Values are not changing

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Visitor
Visitor
1,421 Views
Registered: ‎05-16-2019

You can used this code for IBERT desgn :

# sms.py: class SmsClient: def __init__(self, url, username, password): self.username = username self.password = password def send_sms(phone_number, message): # TODO - write code to send sms pass

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Visitor
Visitor
1,620 Views
Registered: ‎05-10-2019

Will sms pass helps in logging the real-time data?

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Xilinx Employee
Xilinx Employee
1,614 Views
Registered: ‎10-19-2011

Hi @vilashini ,

what values are not changing? time or RX_BER? or both?

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Visitor
Visitor
1,612 Views
Registered: ‎05-10-2019

RX_BER

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Xilinx Employee
Xilinx Employee
1,610 Views
Registered: ‎10-19-2011

Hi @vilashini ,

do you see the value changing in the GUI?

 

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Visitor
Visitor
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Registered: ‎05-10-2019

When I run the Tcl script GUI values also not changing.

But when I stop the Tcl script, RX_BER values are changing in GUI.

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Visitor
Visitor
1,586 Views
Registered: ‎05-10-2019

 
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Visitor
Visitor
1,585 Views
Registered: ‎05-10-2019

Please can you suggest me the solution?

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Explorer
Explorer
1,545 Views
Registered: ‎10-12-2018

Hi,

To use Vivado form python I suggest to use pexpect or wexpect.

To start you can view my cleye project, which is under development, but to goal is to give a handy python wrapper for IBERT, to make the eye more clean, and open.

Xilinx Employee
Xilinx Employee
1,531 Views
Registered: ‎10-19-2011

Hi @vilashini ,

it looks like you are running into the situation that calling your script is seen as a single running command and preventing the IBERT GUI to update values in the mean time. I am not aware of a way to work around this right now. Maybe if you put your script into the background.

Might be that the solution @betontalpfa is recommending would be a better approach here.

As a hint for @betontalpfa , for link tuning exist the bundle of xapp1295/xapp1322, which might interest you and maybe you can add this to your eye cleaner.

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Visitor
Visitor
1,413 Views
Registered: ‎05-10-2019

Do we know the transmitted pattern. Iam generating PRBS- 7 bit. How do we know the sequence of binary data?

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Explorer
Explorer
1,408 Views
Registered: ‎10-12-2018

Take a look at this document (p. 148; chapter: TX Pattern Generator)

image.png

 

Visitor
Visitor
1,402 Views
Registered: ‎05-10-2019

Can we compare the Tx pattern and Rx pattern and calculate the ber manually?

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Visitor
Visitor
1,381 Views
Registered: ‎05-10-2019

I am generating PRBS 7 bit polynomial. How do we know the transmitted binary pattern sequence from the polynomial? What are the seed values chosen?

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Explorer
Explorer
1,369 Views
Registered: ‎10-12-2018

Hi @vilashini 

Note, that the JTAG/TCL much more slower than a transceiver, so it seems (if I understand correctly), that theoretically impossibile to set/store the pattenrs on the fly. What is your usecase? Why do you interested in this?

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Visitor
Visitor
1,365 Views
Registered: ‎05-10-2019

I am going to use it for free space optical communication, where the receiver and transmitter are located on different buildings. So I can't able to loop back the receiver to same FPGA board. So, I manually need to calculate the ber by knowing the TX and RX Pattern.

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Explorer
Explorer
1,356 Views
Registered: ‎10-12-2018

I see.

Shortly:

You dont need to calculate BERT manually, you can use any protocol and the FPGA will calculate the BERT automaticly.

Detail:

Please take a look on the UG476 Transceiver Guide, (RX Margin section). If you understand the structure of the BERT calculation, it does not requiresto know what data is sent over the link

Maybe this post can help you too, where I learnt the same.

Sum:

  1. Load an image containing an IBERT in the FPGA on the both side of the link.
  2. Add manually links in IBERT's GUI in the hardware manager
  3. Set the same pattern on both side (then reset the link. )
  4. You should see link up, with no BERT.

Note, that if you dont use the same pattern the BERT will be calculated correctly, just the GUI will report no link.

 

Visitor
Visitor
1,327 Views
Registered: ‎05-10-2019

  1. Load an image containing an IBERT in the FPGA on both side of the link.

                             Do we have to use two FPGA Boards?

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Explorer
Explorer
1,307 Views
Registered: ‎10-12-2018

You mention that you have two boards in two buildings...

I didn't get the question...

The IBERT module itself does not requires two boards or FPGAs. The endpoints of the link under scope can be in the same FPGA, or in different FPGAs on the same board / same JTAG chain or on different boards / different JTAG chains.

 

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