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384 Views
Registered: ‎03-17-2018

Question about XCKU3P GTY Quad reference clock sharing

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HI, 

I would like to know if it is feasible to use the same reference clock (QPLL) shared between 10 GTY transceivers in 3 different Quads of XCKU3P. In our current design, we would like to use 10 GTY transceivers, and route them all through the FMC connector. in this case, we need to power up 3 quads. Say that, we power on Quads 224, 225 and 226, to get the 10 GTYs in total (2 of the quad 227 GTY kept disabled).

But the problem is that there is only one pair of reference clock can be routed through FMC. so my question is whether we can use the single reference clock from one Quad for all the 10 GTYs? and how much the speed will be compromised? is there a better way to design with regard to FMC routing for multiple Xilinx GTY transceivers?

Thanks any information/insights is appreciated.

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Xilinx Employee
Xilinx Employee
348 Views
Registered: ‎08-07-2007

Re: Question about XCKU3P GTY Quad reference clock sharing

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hi xiaosenjiang@gmail.com 

 

if line rate is lower than 16.375Gbps, then you can share reference clock with two quads above and two quads below. totally 5 quads.

if the line rate is between 16.375 and 28.21Gbps, then you can share reference clock with one quad above and one quad below. totally 3 quads.

if line rate is higher than 28.21Gbps, then no reference clock sharing.

 

so in your case, if you provide reference clock with bank #225 and bank #224 and 226 share that reference clock, you can go to 28.21Gbps.

however, if you provide reference clock to either 224 or 226, then, the max speed is 16.375Gbps.

 

Thanks,

Boris

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3 Replies
Moderator
Moderator
365 Views
Registered: ‎04-12-2017

Re: Question about XCKU3P GTY Quad reference clock sharing

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Hello xiaosenjiang@gmail.com 

Yes, Its possible to share clocks with transceivers placed in other quads with the help of GTSouthrefclk and GTnorthrefclk. 

clk sharin.PNG

 

These rules must be observed when sharing a reference clock to ensure that jitter margins
for high-speed designs are met:
• The number of Quads above the sourcing Quad must not exceed two.
• The number of Quads below the sourcing Quad must not exceed two.
• The total number of Quads sourced by an external clock pin pair (MGTREFCLKN/
MGTERFCLKP) must not exceed five Quads (or 20 transceivers).

This is not very straight forward; so i will recommend you to go through UG578 page 29 Reference Clock Selection and Distribution section for more help.

Thank you 

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358 Views
Registered: ‎03-17-2018

Re: Question about XCKU3P GTY Quad reference clock sharing

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Thanks for the quick response, what is the max speed we can achieve when sharing the clock like the way proposed?

I will read the spec for more info. thanks.

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Xilinx Employee
Xilinx Employee
349 Views
Registered: ‎08-07-2007

Re: Question about XCKU3P GTY Quad reference clock sharing

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hi xiaosenjiang@gmail.com 

 

if line rate is lower than 16.375Gbps, then you can share reference clock with two quads above and two quads below. totally 5 quads.

if the line rate is between 16.375 and 28.21Gbps, then you can share reference clock with one quad above and one quad below. totally 3 quads.

if line rate is higher than 28.21Gbps, then no reference clock sharing.

 

so in your case, if you provide reference clock with bank #225 and bank #224 and 226 share that reference clock, you can go to 28.21Gbps.

however, if you provide reference clock to either 224 or 226, then, the max speed is 16.375Gbps.

 

Thanks,

Boris

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Don't forget to reply, give kudo and accept as solution
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