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Newbie
Newbie
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Registered: ‎03-15-2019

RMS jitter value of XCZU19EG

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Hi,

I am working on  XCZU19EG-2FFVD1760E. I did'nt get the value of RMS jitter of the transciever clock from the documents. Please share RMS jitter maximum value.

 

 

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Moderator
Moderator
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Registered: ‎07-30-2007

We use a phase noise plot to specify the "jitter" component that is allowed.  This is because not all jitter frequencies will be a problem for the GT so that using phase noise may allow the use of a cheaper oscillator.  There are some online phase noise plot to jitter converters that you might use to get a ballpark for what the jitter should be.  You should also be able to get phase noise information from oscillator vendors.




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Moderator
Moderator
458 Views
Registered: ‎07-30-2007

We use a phase noise plot to specify the "jitter" component that is allowed.  This is because not all jitter frequencies will be a problem for the GT so that using phase noise may allow the use of a cheaper oscillator.  There are some online phase noise plot to jitter converters that you might use to get a ballpark for what the jitter should be.  You should also be able to get phase noise information from oscillator vendors.




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Xilinx Employee
Xilinx Employee
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Registered: ‎12-10-2009

The clock reference clock requirements are defined as a phase noise mask. 

GTR is table 61

GTH is table 102

GTY is table 114

http://www.xilinx.com/support/documentation/data_sheets/ds925-zynq-ultrascale-plus.pdf

Thanks.

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Newbie
Newbie
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Registered: ‎03-15-2019

Ok. Got it. Thank you for the explanations.

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