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Newbie sreevm96
Newbie
318 Views
Registered: ‎03-15-2019

RMS jitter value of XCZU19EG

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Hi,

I am working on  XCZU19EG-2FFVD1760E. I did'nt get the value of RMS jitter of the transciever clock from the documents. Please share RMS jitter maximum value.

 

 

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1 Solution

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Moderator
Moderator
272 Views
Registered: ‎07-30-2007

Re: RMS jitter value of XCZU19EG

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We use a phase noise plot to specify the "jitter" component that is allowed.  This is because not all jitter frequencies will be a problem for the GT so that using phase noise may allow the use of a cheaper oscillator.  There are some online phase noise plot to jitter converters that you might use to get a ballpark for what the jitter should be.  You should also be able to get phase noise information from oscillator vendors.

Roy


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3 Replies
Moderator
Moderator
273 Views
Registered: ‎07-30-2007

Re: RMS jitter value of XCZU19EG

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We use a phase noise plot to specify the "jitter" component that is allowed.  This is because not all jitter frequencies will be a problem for the GT so that using phase noise may allow the use of a cheaper oscillator.  There are some online phase noise plot to jitter converters that you might use to get a ballpark for what the jitter should be.  You should also be able to get phase noise information from oscillator vendors.

Roy


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Don't forget to reply, kudo, and accept as solution
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Xilinx Employee
Xilinx Employee
259 Views
Registered: ‎12-10-2009

Re: RMS jitter value of XCZU19EG

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The clock reference clock requirements are defined as a phase noise mask. 

GTR is table 61

GTH is table 102

GTY is table 114

http://www.xilinx.com/support/documentation/data_sheets/ds925-zynq-ultrascale-plus.pdf

Thanks.

Newbie sreevm96
Newbie
236 Views
Registered: ‎03-15-2019

Re: RMS jitter value of XCZU19EG

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Ok. Got it. Thank you for the explanations.

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