01-10-2018 12:09 AM
I've got some problem with my Sata II project. My receiver path was not stable sometimes.
As you can see in figure 1, I don't know why RX_CDR_LOCK was not stable even though I did configure CDR the same as recommend settings in UG_476. Anyway, input signals still seemed to be good when there was no Disparity Err signal. I wondered that did RX_CDR_LOCK signal make sense
and should I do anything to make it look better?
Figure 1: CDR not locked
Another problem I met is Rx buffer was Overflow or Underflow sometimes as Figure 2 below. I did use clock correction, with Align_comma_word = 4, my "clock correction sequence length" = 4 and it's value is "7b4a_4abc".
Could you guys tell me what could lead to this problem and how to fix this please.
01-10-2018 02:22 AM
can please share the following information
1. share the XCI file .
2. Is this issue seen only with One HDD or with other devices
3. is 8/10 encoding is done in PHY layer or is done in the SATA IP core .
4. share the clocking structure details for both the FPGA and HDD or SDD.
01-11-2018 05:23 PM
I attached .xci file and the block design that you can figured out our clocking structures in our project. Some information about the problem we had is:
1. CDR not locked was seen with nearly all devices: SSD, HDD when we tested sata host, and computer also when we tested sata device.
2. Buffer underflow and overflow were seen with sata device only when we tested with several computers.
3. 8b/10b encoding and decoding were done in physical, I mean it was included in GTX transceiver wizards.