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Registered: ‎05-09-2014

Re: Frequency of QPLL clock from a GTX core

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Update:
I ran the Vivado simulations for the SGMII core and the GTX core. The signals QPLLOUTREFCLK_OUT and QPLLOUTCLK_OUT are very different.
For the SGMII core QPLLOUTCLK_OUT is high all the time. QPLLOUTREFCLK_OUT is 125MHz.
For the GTX core QPLLOUTCLK_OUT has a clock with a period of 200ps. QPLLOUTREFCLK_OUT is 156.25MHz.

To me this looks like the QPLL clocks are not compatible. Will this work? How do I fix this?
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @marvinscheinbart ,

correct. If you have the shared logic in example design just comment out the GTXE2_COMMON instantiation. The synthesis will do the rest.

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Moderator
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Registered: ‎07-30-2007

Its not clear to me what problem you expect this to cause.  Can you show more detail of the channel set up on each of these?




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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @marvinscheinbart ,

looks like you took a sgmii core and the default transceiver core.

The sgmii core runs with 1.25Gbps and 125MHz refclk and it is using CPLL.

The transceiver core runs at 10.3125Gbps and a refclk of 156.25MHz and it is using QPLL.

I would say it is quite obvious that they are different. What is your intention on comparing them? Do you try to bring these together?

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Registered: ‎05-09-2014

Eschidi:

     I was given an existing project with the GTX core already in and working.  I was asked to take the existing project and add a Tri-Mode Ethernet MAC and an SGMII interface.  Adding this Ethernet interface would allow the VC707 board to receive Ethernet frames using the RJ-45 connector.

    The Ethernet MAC/SGMII interface uses the 125MHz clocks provided by the board (AH8, AH7). The existing GTX core was created to use a 156.25MHz clock provided by SMA connectors.  The existing design with the 156.25MHz GTX core is already in the field and can not be changed.  I could ask my development partners to change the GTX core frequency to 125MHz but that would require a logic redesign.

    Both the GTX and SGMII cores are in the same tile so they must share the same QPLL logic.  I understand that the QPLL clocks are different and sharing them between the cores will not work.  The GTX core will work but the MAC/SGMII probably will not.  What I'm looking for is a way to make them work together.

    Any help or suggestions would be greatly appreciated.

        Marv

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @marvinscheinbart ,

I do not see that the SGMII core would need the QPLL. I will most likely be setup to use the CPLL. Please check.

With that the two setups can work perfectly in parallel. The only thing you need to consider is the COMMON block instantiation. With using the CPLL the SGMII core does not need the COMMON block. It just adds it as the instantiation is needed to get the quad to work. But as your other GTX design is already using that you can delete its instantiation in the SGMII core.

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Registered: ‎05-09-2014

Eschidi:

     When I bring up the 1G/2.5G Ethernet PCS/PMA or SGMII(16.1)  in the IP generator it gives me two options, Include Shared Logic in Core and Include Shared Logic in Example Design.  The Include Shared Logic in Example design which show QPLLOUTCLK_IN and QPLLOUTREFCLK_IN as inputs.  If I chose Include Shared Logic in Core this shows QPLLOUTCLK_IN and QPLLOUTREFCLK_IN as outputs.

     I usually start from an example design.  I was under the impression that both versions of the core required QPLLOUTCLK_IN and QPLLOUTREFCLK_IN clocks.  Both types of cores has a GTXE2_COMMON that produced these clock signals.  Both of these signals are connected to the PCS_PMA instance.

    Are you saying that for the SGMII interface, I don't need the QPLLOUTCLK_IN and QPLLOUTREFCLK_IN clocks?  Could I remove the GTXT2_COMMON module and leave these ports open? Or grounded?

     Marv

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @marvinscheinbart ,

correct. If you have the shared logic in example design just comment out the GTXE2_COMMON instantiation. The synthesis will do the rest.

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Registered: ‎05-09-2014

Eschidi:

      I made the change you suggested and Vivado processed the design without issue.  I haven't tested the design yet but that will be done on Monday.  I'm going to close this case since Vivado ran fine.

    Thanks for the information and help.  It was much appreciated. 

       Marv

 

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Registered: ‎05-09-2014

Eschidi:

      I marked this issue as solved but I have more information.  I did as you suggested and Vivado completed without issue.  But, when I ran my simulation txoutclk was not output from the PCS_PMA core (a module within the SGMII core) and nothing worked.  After a little experimenting, I had to set both GT0_QPLLOUTCLK_IN and GT0_QPLLOUTREFCLK_IN to zero, then txoutclk worked.  Also, these ports being open caused my simulation run noticably slower.

     I'm going to verify everything works in simulation before I try this on my VC707.  I'll post an update sometime tomorrow.

         Marv

 

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