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Participant
Participant
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Registered: ‎01-17-2018

Recovered clocks from all channels

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I have a system with multiple serial transmitters (not Xilinx FPGAs) running at the same nominal frequency, but all of them with independent (not locked in frequency).

I need to make a ultrascale design which receives the serial links.  In order to properly capture the deserialized data, i imagine i need the recovered clock of each channel.

My intention is to use the recovered clock to write the deserialized data into a dual-clock FIFO, then read the data out of the FIFO with a "system clock".

For a quad, I have generated the GT core (and example design) a few times, but it always appears with one recovered clock, whicle i need 4 of them.

Any advise ?

 

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Moderator
Moderator
515 Views
Registered: ‎07-30-2007

Each transceiver has an RXOUTCLK that would normally drive the RXUSRCLK.  That would be the recovered clock for that channel. 

You are implying that each of your recovered clocks is at a different or slightly different frequency.  If this is the case they each need to drive their own RXUSRCLK with their own RXOUTCLK.  You would need to do a different wizard instantiation for each transceiver for this to happen.  Or you could modify the USRCLK routing yourself.

 




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Participant
Participant
582 Views
Registered: ‎01-17-2018

I have found by myself the answer.

In thGT wizard,  in the Structural Option, All ports, there is the port:

   rxrecclkout_out.

If i check mark it, i get all the recCLKs exposed.

Participant
Participant
541 Views
Registered: ‎01-17-2018

i still have problems. I now have a design with a GT quad, and all four recCLKs coming out of the core .

However as soon as i use them to clock other circuits (in my case ILAs), i get the error:

[DRC RTSTAT-1] Unrouted nets: 4 net(s) are unrouted. The problem bus(es) and/or net(s) are
 example_wrapper_inst/gtwizard_ultrascale_0_inst/inst/gen_gtwizard_gthe3_top.gtwizard_ultrascale_0_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[32].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxrecclkout_out[3:0].

Then i have tried to add a  BUFG_GT to each recovered clock (between source and destination) and i still get the same error.

there is also a Critical warning:

[Route 35-7] Design has 8 unroutable pins, potentially caused by placement issues.

 

What is needed to use all recCLKs outside of a GT ?

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Moderator
Moderator
527 Views
Registered: ‎07-30-2007

A recovered clock cannot drive an ILA because it will not be present at power up.  You need to use a free running clock to drive ILA's.  Usually for GT's you can use the refclk to drive an ILA.  Use the ODIV2 output of the IBUFDS_GTE* to BUFG_GT to ILA.

The recovered clock you discovered is inside the hard block and can only drive an external refclk pin.  It is not able to drive the fabric as you discovered.  The RXUSRCLK's are usually driven by the recovered clock as long as the RXOUTCLKSEL is not 011 or 100.




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Participant
Participant
521 Views
Registered: ‎01-17-2018

thanks for explaining that the recovered clock from inside the hard block can only drive an external refclk pin, this was not obvious from the GUI, example design or documentation.

You suggest using the RXUSRCLK, however as far as i can see there are only two of them (RXUSRCLK and RXUSRCLK2) per quad. I need the all the four independent recovered clocks from my GT core.

 

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Moderator
Moderator
516 Views
Registered: ‎07-30-2007

Each transceiver has an RXOUTCLK that would normally drive the RXUSRCLK.  That would be the recovered clock for that channel. 

You are implying that each of your recovered clocks is at a different or slightly different frequency.  If this is the case they each need to drive their own RXUSRCLK with their own RXOUTCLK.  You would need to do a different wizard instantiation for each transceiver for this to happen.  Or you could modify the USRCLK routing yourself.

 




----------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution
----------------------------------------------------------------------------


View solution in original post

Participant
Participant
328 Views
Registered: ‎01-17-2018

by doing do a different wizard instantiation for each transceiver, i have been able to implement and test a design where each GT core outputs the recovered clock, in a form usable by the user logic.

So the problems seems to be solved

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