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Adventurer
Adventurer
650 Views
Registered: ‎11-23-2018

Registers for serial line analog parameter

We are facing the issue with data corruption at RX side with GTH transceiver when testing with the actual asynchronous transmitter.

can anyone suggest me which analog parameter(DRP attributes) needs to change to get proper data at RX serial line? We carried out testing with different cables & observed with small length cable we have good results for data not as expected but few bytes are received fine.

please guide me on which DRP attributes needs to be modified?

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13 Replies
Xilinx Employee
Xilinx Employee
634 Views
Registered: ‎03-30-2016

Re: Registers for serial line analog parameter

Hello @verilog_bee 

Please find out what is happening on your HW first, before doing any parameter tuning.
We cannot recommend doing GTH parameter-tuning blindly, because it will take you nowhere.

1. Can you please share the simple schematic of your system ?
- Are you using the same OSC/PLL model to generate REFCLK ?
- How much REFCLK frequency offset between TX/RX ?
- Is SSC enabled or disabled ?
Simple_connectivity_pict.png

2. Is RXBYTEISALIGNED always asserted high ?

3. Are you using 8B10B encoding ?
( If yes, please monitor (RXCTRL3) for not-in-table error , and (RXCTRL1) for disparity error )

4. Please monitor RXBUFSTATUS[2:0] , Do you see any elastic-buffer overflow/underflow ?

5. Do you the insertion-loss value on your channel ?
   ( Perhaps you will modify equalizer mode and IL value setting in GUI here )
    WIZARD_SETTING.png

6. Could you please share EyeDiagram of your input signal at GTH RX pins ?
7. Are you using AC-coupling interconnectivity ?


Thanks & regards
Leo

Adventurer
Adventurer
617 Views
Registered: ‎11-23-2018

Re: Registers for serial line analog parameter

Can you please share the simple schematic of your system?

Your assumption is perfect for schematic. we have USB HOST(PC) as the third-party transmitter.

 
Are you using the same OSC/PLL model to generate REFCLK?

No.
How much REFCLK frequency offset between TX/RX?

I have no idea about PPM offset difference.


Is SSC enabled or disabled?

As we configured GTH from scratch SSC option is greyed out in GUI. please find the attachment for the GTH configuration.

2. Is RXBYTEISALIGNED always asserted high?

With actual HOST it gives pulse whenever data comes proper with the comma(0xbc) character.

with loopback, it continuously stays HIGH.

Are you using 8B10B encoding?
( If yes, please monitor (RXCTRL3) for not-in-table error, and (RXCTRL1) for disparity error )

We continuously monitor these signal using ILA. with HOST disparity error & not valid character both comes. but with loopback it works perfectly, there is no disparity error or valid character issue.

Please monitor RXBUFSTATUS[2:0], Do you see any elastic-buffer overflow/underflow?

Yes, we monitor RXBUFSTATUS[2:0], there is no sign of under/overflow of RX elastic buffer.

Do you the insertion-loss value on your channel?

No. but we are using 1meter length cable. and as per specs, it is near about 7 db.

 Could you please share EyeDiagram of your input signal at GTH RX pins?

Yes, I thought about eye diagramme & have an instance of in-system IBERT, but we have DRP FSM too which is required to run dynamically. so simultaneously I can not run IBERT as well as DRP. for eyescane DRP port of IBERT should be connected to GTH right?

Are you using AC-coupling interconnectivity?

Yes, you can see it in the shared screenshots.

 

   

 

 

 

 

Capturess1.JPG
Capturess2.JPG
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Xilinx Employee
Xilinx Employee
591 Views
Registered: ‎03-30-2016

Re: Registers for serial line analog parameter

Hello @verilog_bee 

1. I believe LPM setting will perform better, rather than DFE.
    So, please try to set "Equalization mode" to LPM.

2. Please set IL to more realistic value also to fit your system.
   ( Let say 12 dB, since you also need to consider insertion loss of connectors and board )

3. You mentioned that RXBYTEALIGNED is not stable high, non-in-table and disparity errors occur alot.
So, I am suspecting that you have a Signal-Integrity problem here.
If you do not have EyeDiagram from IBERT to share,
Could you please get EyeDiagram using oscilloscope ? ( try to probe signal near GTH RX pins)

4. (Most likely) your HW will have REFCLK frequency offset since you are using asynchronous clock.
Knowing TX/RX REFCLK maximum frequency offset on your system is very important.
Right now, you set "0" in your GTH transceiver. You will need to set approriate value for your system.
Or else GTH will not link-up properly.

Hope this helps.

Regards
Leo

Adventurer
Adventurer
529 Views
Registered: ‎11-23-2018

Re: Registers for serial line analog parameter

Hello @karnanl 

We highly appreciate your quick response.

Let us test the design with your suggested solution. I will get back to you soon.

Adventurer
Adventurer
473 Views
Registered: ‎11-23-2018

Re: Registers for serial line analog parameter

Hello @karnanl 

1. I believe LPM setting will perform better, rather than DFE.
    So, please try to set "Equalization mode" to LPM.

We applied LPM mode, data gets corrupted.

2. Please set IL to more realistic value also to fit your system.
   ( Let say 12 dB, since you also need to consider insertion loss of connectors and board )

Earlier we used the default setting of insertion loss which is at 20 dB. After your suggestion, we estimated the loss & it is near about 10 db. With 10 dB we also observed the improved data at RX side.  

3. You mentioned that RXBYTEALIGNED is not stable high, non-in-table and disparity errors occur alot.
So, I am suspecting that you have a Signal-Integrity problem here.
If you do not have EyeDiagram from IBERT to share,
Could you please get EyeDiagram using oscilloscope ? ( try to probe signal near GTH RX pins)

We carried out the test using IBERT example design for our physical transmission medium with loopback. Eye-opening is nearer to 70 %.

4. (Most likely) your HW will have REFCLK frequency offset since you are using the asynchronous clock.
Knowing TX/RX REFCLK maximum frequency offset on your system is very important.
Right now, you set "0" in your GTH transceiver. You will need to set approriate value for your system.
Or else GTH will not link-up properly.

We set 200 ppm value which is maximum at the required line rate.

With all the above testing, still, we are not receiving the expected data.

Regards

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Xilinx Employee
Xilinx Employee
436 Views
Registered: ‎03-30-2016

Re: Registers for serial line analog parameter

Hello @verilog_bee 

>We applied LPM mode, data gets corrupted.

Which EQ setting is performing better ? ( DFE or LPM ? )

>Are you using AC-coupling interconnectivity?
>Yes, you can see it in the shared screenshots.

Yes, I can see that your transceiver is using "Link coupling =AC" setting.
But do you also implement AC coupling on your board ?
USB_HOST_error.png

> We carried out the test using IBERT example design for our physical transmission medium with loopback. Eye-opening is nearer to 70 %.

70% should be good enough. Could you please share the screenshot capture ?

-- I believe you are doing external loopback from GTH TX --> GTH RX, something like this

USB_HOST_looback.png

     "TX->connector->Cable->connector->RX" loopback as mentioned above can be used to check if your board / cable is good or not.
     But I think you also need to check IBERT Eye Diagram with serial input signal from USB Host.
     Is it possible ?

Thanks
Leo

 

Xilinx Employee
Xilinx Employee
423 Views
Registered: ‎10-19-2011

Re: Registers for serial line analog parameter

hi @verilog_bee ,

my suspicion is that the CDR cannot follow the SSC used in USB with your setup. Would you be able to switch off SSC in the USB host for testing?

To get a correct CDR setting you would need to put the downspread of 5000 in the wizard GUI for generation.

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Adventurer
Adventurer
344 Views
Registered: ‎11-23-2018

Re: Registers for serial line analog parameter

Hello @karnanl 

We applied LPM mode, data gets corrupted.

LPM

But do you also implement AC coupling on your board ?

Connector(on FMC) => TPD4E02B04 4-Channel ESD Protection Diode => 0R resistor => capacitor(in series )  => IC => FM connector =>  FPGA pin

I believe you are doing external loopback from GTH TX --> GTH RX, something like this

AC coupling capacitor is not there at RX side. we have it on TX side only.

But I think you also need to check IBERT Eye Diagram with serial input signal from USB Host.
     Is it possible ?

Yes, we can try this. can you please guide me how I can carry out the EYEscan on my design with actual USB HOST. We don't have High freq. CRO/ analyser for eye-scanning.

My design uses DRP port for reconfiguration in run time. I tried to implement the in system IBERT. But as per my knowledge, the in system IBERT use DRP port for EYESCANIG so how it is possible to provide the DRP control to IBERT in run time?

 

 

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Adventurer
Adventurer
341 Views
Registered: ‎11-23-2018

Re: Registers for serial line analog parameter

Hello @eschidl 

 Would you be able to switch off SSC in the USB host for testing

USB HOST is not in control of mine.

To get a correct CDR setting you would need to put the down spread of 5000 in the wizard GUI for generation ?

did u want me to change the spread spectrum clocking to 5000?

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Xilinx Employee
Xilinx Employee
287 Views
Registered: ‎03-30-2016

Re: Registers for serial line analog parameter

Hello @verilog_bee 

>Yes, we can try this. can you please guide me how I can carry out the EYEscan on my design with actual USB HOST. We don't have High freq. CRO/ analyser for eye-scanning.

Hmm, I just realized that USB protocol has to exchange handshaking packet before procedding to data payload transfer. Since Xilinx IBERT cannot response to Host USB, I don't think my proposal is possible to do. Pardon me for the confussion.

>My design uses DRP port for reconfiguration in run time. I tried to implement the in system IBERT. But as per my knowledge, the in system IBERT use DRP port for EYESCANIG so how it is possible to provide the DRP control to IBERT in run time?

Unfortunately, In-System IBERT needs to control GTH channel DRP I/F to do the job.
# I am not sure if we can do it manually, there will be some confict accessing transceiver DRP I/F.

>Connector(on FMC) => TPD4E02B04 4-Channel ESD Protection Diode => 0R resistor => capacitor(in series ) => IC => FM connector => FPGA pin
> AC coupling capacitor is not there at RX side. we have it on TX side only.

I can see that your are connecting an IC to FPGA GTH RX pin directly without AC coupling.
Could you please confirmed that your IC output signal common-mode voltage is within GTH RX spec ?

>>To get a correct CDR setting you would need to put the down spread of 5000 in the wizard GUI for generation ?
>did u want me to change the spread spectrum clocking to 5000?

Yes, I believe @eschidl  is asking to set SSC setting in the GUI to 5000 , since you cannot turn it off in your Host setting.. This proposal may solve your issue.


Thanks & regards
Leo

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Adventurer
Adventurer
243 Views
Registered: ‎11-23-2018

Re: Registers for serial line analog parameter

Hello@karnanl@eschidl 

I can see that you are connecting an IC to FPGA GTH RX pin directly without AC coupling.

Sorry, I misunderstood, there is a coupling capacitor in the path before it goes to FPGA.
Could you please confirm that your IC output signal common-mode voltage is within GTH RX spec ?

Yes, It is in range.

@eschidl 

As you can see the screenshots in earlier reply of mine that the SSC tab greyed out(Disabled), so unable to put the value of 5000. Is there any other way to provide value of "SSC" & "PPM difference between the TX & RX"  to GTH means via DRP interface?

what I am suspecting is that data corruption is very relevant to SSC & PPM differences. Please guide me to modify the value of these attributes.

Regards.

 

 

 

 

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Xilinx Employee
Xilinx Employee
227 Views
Registered: ‎03-30-2016

Re: Registers for serial line analog parameter


Hello @verilog_bee 

>there is a coupling capacitor in the path before it goes to FPGA.

Thank you. It should be no issue.

>Yes, It is in range.

Thank you for confirming. No issue.

>As you can see the screenshots in earlier reply of mine that the SSC tab greyed out(Disabled), so unable to put the value of 5000. Is there any other way to provide value of "SSC" & "PPM difference between the TX & RX" to GTH means via DRP interface?

SSC setting is only valid for 1.5, 3, 6Gbps (targetting SATA ).
SSC.png

BTW, did you aware that GTH/GTY does not support USB ?

SupportedProtocol.png

Thanks
Leo

 

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Adventurer
Adventurer
218 Views
Registered: ‎11-23-2018

Re: Registers for serial line analog parameter

BTW, did you aware that GTH/GTY does not support USB?

Of course, I know.
 
Meanwhile, I changed literate to 5gbps. SSC is enabled & set to 5000 in GUI. Now data captured at RX is perfect.
 
The only concern I have is that can you help me out for DRP attributes of SSC & PPM difference? so I can manage these value of down spread using DRP interface.
 
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