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Visitor
Visitor
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Registered: ‎04-02-2020

RocketIO Transciver SIS Kit for HyperLynx

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Can't probe signals - see attached document.

 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-01-2017

Yes, probing U2 at die is the same as probing the output of the equalizer.

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @chongkim_ngc 

Are you using IBIS-AMI model from the following link ?

If this is the case, Please see also UG587/UG588.
These IBIS-AMI models are designed to work with older version of SiSoft tool. It will not work with the latest ADS, HyperLinx.

V5_IBIS_AMI.png

 

BTW, I do no see any internal milestone for updating this IBIS-AMI models.

Thanks & regards
Leo

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Visitor
Visitor
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Registered: ‎04-02-2020

I am using rio_sis_kit_2_0.  See below.

 

** ____ ____
** / /\/ /
** /___/ \ / Vendor: Xilinx
** \ \ \/ Version: 2.0
** \ \ Filename: readme.txt
** / / Date Last Modified: January 8 2009
** /___/ /\ Date Created: January 8 2009
** \ \ / \
** \___\/\___\
**
** Device: Virtex-5 LXT, SXT and FXT
** Purpose: RocketIO GTP Transceiver and GTX Transceiver
** for Mentor Graphics HyperLynx
** Revision History: Initial

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-01-2017

I downloaded the Eldo model from this link, which looks to be the same one as what you are using:

https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/device-models/hspice-and-eldo-models/virtex-series-fpgas.html

I just double clicked on the .ffs file and it launches in Hyperlynx. I tried V8.2.1 and VX.2.4, and both simulated successfully. On the right side, "Eldo/ADMS" must be selected for V8.2.1.

Did you just run the testbench as-is or have you made changes to the design? If so, go back to the original .ffs file to see if you can run it successfully?

Here is my screenshot from VX.2.4:

image.png

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Visitor
Visitor
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Registered: ‎04-02-2020

I was able to probe MGTRXOUTP/N_V5_GTX(at pin), but I am not sure what should the acceptable equalizer output voltage level be - see attached document.   In other words, what does the CDR expect from the equalizer?

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-01-2017

10mVdiff does not look right.

The example design has 400mVdiff eye opening.

Have you tried the example and do you get similar eyes? What's different in your design compared to the example?

image.png

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Visitor
Visitor
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Registered: ‎04-02-2020

The issue is not about probing at RX pins.  What I want to see is the output of RX equalizer, MGTRXOUTP_V5_GTP(at pin) and MGTRXOUTN_V5_GTP(at pin).  See attached document for detailed explanations.  In brief, try to probe the equalizer outputs and let me know if you can see a reasonable the eye diagram.

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-01-2017

I thought in your "‎04-08-2020 04:20 PM" reply you were able to probe the U2 "at the die" eye diagram, which is the internal eye after RX equalizer, which is the "equalizer outputs" that you are looking to probe. Did I miss understand something?

In your "‎04-08-2020 04:20 PM" attachment, the equalizer output shows only 10mVdiff opening, which is what I was concerning. The example testbench had 400mVdiff opening.

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Visitor
Visitor
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Registered: ‎04-02-2020

So, are you saying that probing U2 at die is the same as probing the output of the equalizer?

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-01-2017

Yes, probing U2 at die is the same as probing the output of the equalizer.

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Visitor
Visitor
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Registered: ‎04-02-2020

Excellent!  I accept your solution and appreciate your support very much.  I wish it came a little earlier.  That is why I miss the person-to-person hot line support that Xilinx used offered. Well, I guess it's all about a cost cutting measure.

Regards,

chong

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Visitor
Visitor
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Registered: ‎04-02-2020

Although I've accept your solution, I forgot to ask you the following question:

If probing at the RX pin die is the same as probing at the output of the equalizer, why changing the equalizer from 0 to 3 does not affect the output of the equalizer.

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Xilinx Employee
Xilinx Employee
635 Views
Registered: ‎06-01-2017

You are right! I am seeing the same results across RXEQ settings as well.

I went back to Hyperlynx V8.2.1 and the red SPICE probes showed up. The external pins have identical results when changing RXEQ setting, but the red SPICE probes changed. The "always at the die" setting does not seem to be in effect.

The red SPICE probes are not there in VX.2.4 and at this point I have to say it's a tool compatibility issue. My recommendation is to go back to v8.2.1 to simulate with our eldo models.

I am not sure about your eldo model usage since I am not familiar with eldo models. Typically, IBIS-AMI models are used for channel simulation purposes (as opposed to eldo), and we do also provide IBIS-AMI models for v5 GTX/GTP. They can be downloaded from here: https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/device-models/ibis-ami/virtex-series-fpgas.html

If you have concerns moving back to v8.2.1, I would suggest you try IBIS-AMI model.

By the way, in IBIS-AMI simulation environment, the Hyperlynx "always at the pin" vs "always at the die" setting determines whether the RX is probed at the pin or at the equalizer output, thus I was confused with the Eldo usage.

 

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Visitor
Visitor
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Registered: ‎04-02-2020

Seems like you have V8.2.1.  Can you kindly run a simulation and probe the equalizer with the setting of 0 and 3?  Let me know the differential eye height of the equalizer for each case.  Set the TX driver to 0, meaning the output swing = 0 and pre-emphasis = 0.

 

Thanks,

Chong

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-01-2017

Red = RX input pin

Blue = RXEQ output (setting = 0)

Green = RXEQ output (setting = 3)

I recommend for you to try IBIS-AMI model.

image.png

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Visitor
Visitor
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Registered: ‎04-02-2020

Excellent!  Can you show me a screen shot of the schematic for this simulation?  In addition, it would be great to understand how the TX and RX are configured.  Thanks in advance.

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-01-2017

It's identical to UG512. All settings are as set by the example testbench .ffs. I only changed RXEQ between 0 and 3 for you to see the difference. I recommend for you to get the tool so that you can evaluate link margin for your actual system.

image.png

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Visitor
Visitor
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Registered: ‎04-02-2020

Fantastic support and excellent trouble shooting.  Completely accept the recommendation as the solution without any further questions.

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