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Visitor batowe
Visitor
126 Views
Registered: ‎07-16-2019

SPDIF RX IP not working on Basys 3

Hi, I am attempting to implement an S/PDIF IP receiver on a Basys 3 development board as part of a degree research project and am encountering some problems which I could really do with some help with.

Essentially, I cannot get the SPDIF to output anything, either in RX or TX mode. I have built a hardware SPDIF to logic level converter on a separate PCB to capture the source SPDIF coaxial signal and have verified that this is working correctly and being input to the Basys 3 board (a positive edge on the coaxial signal produces a positive 3.3v logic edge on the Basys board, verified by feeding this back out through another header pin). My SPDIF signal is coming from a Windows PC and is verified OK (it works if input to a DAC). I am certain that my converter is not dropping any bits (have analysed on an oscilloscope and it works faithfully).

I have tried all manner of clock combinations (the master clock is the Basys' 100MHz master, which I have verified is working correctly) and reset sources, but nothing will make the receiver output any data. Same with the resets, nothing works no matter whether I feed them through a master reset IP module, switches or constant sources.

 

My questions:

Do I need to connect an AXI4_LITE bus even if I just want to perform passthrough to another stream interface?

IS it OK to provide the rx module an SPDIF from an arbitrary I/O pin or does it need to be a particular type of bus?

I am presuming that the rx module should generate an rxclk as long as it sees a valid input?

Is my SPDIF conversion correct (i.e. a positive edge on the coax generates a positive edge on the logic and vice-versa)?

Does anybody have a working block diagram topology that they would be willing to share?

 

Many thanks for any suggestions.

vivado_spdif_bd.png
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Visitor batowe
Visitor
72 Views
Registered: ‎07-16-2019

Re: SPDIF RX IP not working on Basys 3

Worked it out. I wasn't configuring the module correctly at startup. Solved with a JTAG to AXI master to perform register configuration. Perseverence and a sharp learning curve!
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