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stefangriebel
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Registered: ‎11-09-2011

SRIO Internal Loopback, near-end PMA unreliable

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I have a Kintex Ultrascale (ku060) on a custom board and have been unable to get SRIO near-end PMA loopback working reliably. I suspect the reset sequence for the following reasons:

  • I have no issues in simulation for near-end PMA loopback (or external loopback with tx/rx connected in my testbench)
  • Near-end PCS loopback works every time.
  • Using standalone IBERT (no other design in the fabric) I get 0 BERs on all GTY lanes and wide-open eyes.
  • Using In-System IBERTs, on a 4-lane link, not all eyes are open, and the eye quality from lane-to-lane changes from reset to reset sporadically.
  • Sometimes after an SRIO sys_rst, I get link_initialized and port_initialized, but mode_1x = 1. Not all lanes aligned. And sometimes the link_init and mode_1x will fluctate for 1 or 2 of my SRIO cores.

I am using Vivado 2019.1, and the SRIO Gen2 Endpoint v4.1. I have 3 SRIO cores on quads 126, 127, and 128 with the mgt_clk coming in on quad 127 at 156.25 MHz, for 3.125 Gsps, 4-lane SRIO link. I have tried using the clock/reset logic in the core on quad 127, then feeding its reset outputs etc to quads 126 and 128, and I have also tried making the clock/reset logic external to any SRIO cores, and controlling the various resets to each core independently. Both methods give the same result of sporadic link instability on one or more of the cores.

Core 0 = Quad 126
Core 1 = Quad 127
Core 2 = Quad 128

All cores are configured identically, but in the waves we see that the disperr_o output toggling on Core 0, as well as the mode_1x being high while Cores 1 and 2 seem to behave normally in this capture.

disperr_and_mode1x_quad126.png

We also see that Core 0 doesn't have all channels aligned based on the PhyDebug outputs:

PhyDebug_Core0_mode1x.png

 What is the next step in the debug process?

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roym
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Registered: ‎07-30-2007

i would say there are couple of possibilities.

1 You are over equalizing in this mode.  You may need to change to LPM mode and if that isn't enough you would set equalization to a minimum:

RXDFELPM_KL_CFG0, RXLPM_KH_CFG0 set to 0.and RX_OS_CFG0 is set to 1000000 (neutral)

See UG576 page 195.

the other possibility is the far end of the link is interfering and needs to be disconnected or have the amplitude turned down.




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roym
Moderator
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Registered: ‎07-30-2007

i would say there are couple of possibilities.

1 You are over equalizing in this mode.  You may need to change to LPM mode and if that isn't enough you would set equalization to a minimum:

RXDFELPM_KL_CFG0, RXLPM_KH_CFG0 set to 0.and RX_OS_CFG0 is set to 1000000 (neutral)

See UG576 page 195.

the other possibility is the far end of the link is interfering and needs to be disconnected or have the amplitude turned down.




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Don't forget to reply, kudo, and accept as solution
Be sure to visit the Resources post periodically to keep up with the latest
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stefangriebel
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Registered: ‎11-09-2011

My design instantiates the SRIO IP in a Vivado block-diagram.It looks like I have access to the the DFE vs. LPM mode (I will try that) but not access to the RX Equalizer ports required to set equalization to a minimum. Is there an easy way (or any way at all?) to access the RX Equalizer ports from this level? Is it a few bits from one of the TRANSCEIVER_DEBUG ports? 

srio_core_bd_inputs.png

 Also, in my hardware, the far end link is disconnected. I do have a loopback connector board to connect rx/tx outputs directly at the board level, but that is even more unreliable than the PMA internal loopback. Perhaps for the same reasons...

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stefangriebel
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Registered: ‎11-09-2011
Ah the DRP bus is a ganged version for all 4 GTs. Looks like I can access all the low-level settings there.