SSC support GTY Transceiver

[timi]

Hi,

I have a Kintex Ultrascale + device(KU3P) running a custom protocol @ 12.5 Gbit/s  8b/10b encoding.

Does the Transceiver support tx and rx spread spectrum clocking? 

The design is only for loopback(outside FPGA, only one FPGA) intended:

FPGA_TX(Pattern Generator) -> Custom ASIC -> FPGA RX(Pattern Checker)

If both TX and RX support SSC, is it sufficient to have one ssc oscillator for both tx and rx qpll ref clock?

Thank you.

[csattar]

hi @timi,

thanks for contacting Xilinx forums .

from your query I believe and assume you would like whether spread spectrum clocking is supported on GTY transceivers on both  TX and RX .

yes is supported but only on the RX side for this information I would suggest you refer the Table 71: GTY Transceiver Receiver Switching Characteristics of the  ds922 .https://www.xilinx.com/support/documentation/data_sheets/ds922-kintex-ultrascale-plus.pdf.

the SSC support on a specific device is based on characterization.

Xilinx runs characterization for the protocols that are popularly used based on market evaluation.

please refer to the protocols supported list in datasheet.

for example, table Table 70 in ds922 listed the protocols supported by Kintex Ultrascale Plus GTY.

If this list, you can find PCIe Gen1,2,3 and SATA Gen1,2,3. Those protocols claimed SSC.

we can support the SSC defined in these protocols in order to be compliant.

however, in other scenarios beyond the protocols list, we didn't run characterization so we don't support those.

the supported protocols list could vary according to the demands from markets.

let me know your inputs 

Chandra 

if your query is solved please close this thread by accepting the solution 

[timi]

hi @csattar

thank you for the reply.

I thought I can just supply a ssc oscillator clock to the tx Transceiver ref clk and thereby generate the modulated jitter on the data!  So this not possible?

Since the Transceiver support different protocols(and ssc e.g. pcie) should it also support on the tx side?

Thanks

[chsdkj]

timi,

While it is possible that using an SSC oscillator to produce the ref clk that the xcvr TX would use could work (due to the SSC frequency (presumably being 30-33KHz) being much lower than the xcvr PLL bandwidth (>1 MHz (presumably)), support for xcvr RX SSC on the incoming serial data is apparently much more of an issue.

Regardless of what DS922 appears to claim regarding SSC support, documentation for the US xcvr Wizard (PG182, v1.7) shows (p.87) that there is limited (i.e., no) support (officially) for anything other than 1.5, 3 and 6Gbps 8b10b SATA (or similar) protocols, at least if the timing of the incoming datastream is completely unrelated to the local ref clk timing (frequency and phase).  There certainly appears to be no (official) support for SSC RX for datarates of above 6Gbps, with even less support provided if the protocol is something other than 8b10b.

[borisq]

hi @timi 

for tx side, it is also supported. i.e., if the ref clock is SSC modulated, then the tx output data is SSC.

assuming SSC is modulated at low frequency like 33Khz.

Thanks,

Boris

[jlantz · Accepted solution]

SSC support is defined in table 71 of DS922.  Both devices should use the same oscillator and it limited to the lower data rates.

In the advanced section on the GT Wizard the SSC settings can be chosen.

http://www.xilinx.com/support/documentation/ip_documentation/gtwizard_ultrascale/v1_7/pg182-gtwizard-ultrascale.pdf

http://www.xilinx.com/support/documentation/data_sheets/ds922-kintex-ultrascale-plus.pdf