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Observer
Observer
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Registered: ‎09-17-2018

Scrambled data on GTX

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HI!

I am trying to use GTX transceivers on the ZC706 board (1.0625Gb/s with 8b\10b encoding). Unfortunately my oscilloscope could not detect any valid data (after decoding) I was sending. Then I added RX part of the GTX to debug it and now I have more troubles.

In the attached file "gtx_data" is the data from the logic to the GTX before the 8b\10b coding and "rx_data_out" is the received data after 8b\10b decoding.

gtx_tx_rx.png

As you can see there is no pattern in the received data. TX and RX SMA are connected on the board via short cables.

The gtx wrapper and gtx wizard settings are attached.

Thanks for any suggestions in advance!

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Observer
Observer
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Registered: ‎09-17-2018

Re: Scrambled data on GTX

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I fixed timing closure with xpm_cdc_sync_rst, xpm_cdc_array_single modules.

Also I rewrote the initialization sequence and used txuserclk2 instead of txuserclk1.

The sending\receiving loopback in the hardware is working. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Re: Scrambled data on GTX

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Hi @alexeytea ,

did you try your setup in simulation first? Was it working here?

In your setup I would recommend you select ENPCOMMAALIGN, ENMCOMMAALIGN, RXBYTEISALIGN, RXBYTEREALIGN and RXCOMMADET in the wizard additionally. These signals will be needed for comma detection and alignment.

To rule out the wire connection you could use near end PMA loopback in HW first.

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Observer
Observer
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Registered: ‎09-17-2018

Re: Scrambled data on GTX

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@eschidl 
Thanks for the advice. Unfortunately I ran stright into the implementation without simulating it first.

The simulation revealed a bug with my reset circuit, which was asserting reset periodically. That was fixed.

But now I have another problem: gtx is just not working in the simulation, usrclk is not generated, tx_p/tx_n are always "1".
Also in the wrapper txuserrdy is "1" but in the deeper levels txuserrdy_i and txuserrdy_t are "Z".

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

Re: Scrambled data on GTX

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hi @alexeytea 

 

did you check the CPLLLOCK?

if a MMCM is instantiated, does MMCM LOCK assert?

 

you can generate an example design with the .xci file of IP, and run simulation.

 

Thanks,

Boris

 

Thanks,

Boris

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Observer
Observer
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Registered: ‎09-17-2018

Re: Scrambled data on GTX

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@borisq, hello!

Yes, CPLLLOCK goes high in the hardware when I apply clock from Si5324 on the board (212.5 MHz).

 

The generated example design is passing the test.

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Observer
Observer
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Registered: ‎09-17-2018

Re: Scrambled data on GTX

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I forgot to mention, maybe this is crucial:

I've got failed timing reports between "tx_fsm_reset_done" from GTX and FIFO register in my design (-3ns setup).

I assumed the reason is the debug cores, but I can be wrong.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

Re: Scrambled data on GTX

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hi @alexeytea 

 

if simulation fails, i would suggest you fix the issue in simulation first.

is CPLLLOCK asserted in simulation?

where is the tx_startup fsm stuck at in simulation?

 

Thanks,

Boris

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Observer
Observer
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Registered: ‎09-17-2018

Re: Scrambled data on GTX

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@borisq wrote:

hi @alexeytea 

 

if simulation fails, i would suggest you fix the issue in simulation first.

is CPLLLOCK asserted in simulation?

where is the tx_startup fsm stuck at in simulation?

 

Thanks,

Boris


@borisq, sorry for the delayed answer.

I could not make GTX working in the simulation, usrclk is always LOW, tx_fsm_reset_done_out is LOW either.

CPLLLOCK is asserted.

tx_state is "0".

I cannot find tx_startup in the GTX, could you specify the block?
Asserting soft_reset_tx_in gives no affect.

The example design is not starting either.

 

The main concern in sysclk_in. I connected it to the core, toggling it from the testbench, but in the waveform sysclk_in in the GTX asserted high once and goes LOW forever.

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Registered: ‎07-23-2019

Re: Scrambled data on GTX

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I've got failed timing reports between "tx_fsm_reset_done" from GTX and FIFO register in my design (-3ns setup).

If you have timing failures, don't expect things to work in actual silicon. Even if it does on your desk, it won't work reliably in field conditions. Timing closure is a must, not a nice to have.

 

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Adventurer
Adventurer
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Registered: ‎05-07-2018

Re: Scrambled data on GTX

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Hi,

I worked with this Ipcore a lot.

If your simulation does not give you the true answer, then it is impossible to get the right answer on hardware.

try to solve the problem on the simulation part first.

 

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Xilinx Employee
Xilinx Employee
481 Views
Registered: ‎08-07-2007

Re: Scrambled data on GTX

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hi @alexeytea 

 

you can start with the example design.

first, you may have to check the ENPCOMMAALIGN and ENMCOMMAALIGN.

right click on the new xci file, and select 'open IP example design'.

Run simulation and see if it works.

 

if it works, you can modify the frame gen and frame check as needed in your own application.

 

simulation and timing closure have to be pass before going to hardware.

 

Thanks,

Boris

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Observer
Observer
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Registered: ‎09-17-2018

Re: Scrambled data on GTX

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@borisq wrote:

hi @alexeytea 

 

you can start with the example design.

first, you may have to check the ENPCOMMAALIGN and ENMCOMMAALIGN.

right click on the new xci file, and select 'open IP example design'.

Run simulation and see if it works.

 

if it works, you can modify the frame gen and frame check as needed in your own application.

 

simulation and timing closure have to be pass before going to hardware.

 

Thanks,

Boris


@borisq, I added DRP, powerdown and PRBS ports in GTX wizard and the core in the example design started to work (usrclk and txn_out are generating), don't know exactly why. 
Thanks! 

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Observer
Observer
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Registered: ‎09-17-2018

Re: Scrambled data on GTX

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I fixed timing closure with xpm_cdc_sync_rst, xpm_cdc_array_single modules.

Also I rewrote the initialization sequence and used txuserclk2 instead of txuserclk1.

The sending\receiving loopback in the hardware is working. 

View solution in original post

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Registered: ‎07-23-2019

Re: Scrambled data on GTX

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congrats, but the meaning and usefulness of a forum is to share problems to find a solution collectively and help others in the future.

you just say 'I changed something and it works'. That won't help anyone else. In fact, it will be a waste of time.

Whenever I post a problem here, if I find the solution myself, I spare some time writing the detailed solution to help others in return for the help I expect from others.

Givers need takers, is just not being a taker all the time.

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Observer
Observer
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Registered: ‎09-17-2018

Re: Scrambled data on GTX

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@archangel-lightworks wrote:

congrats, but the meaning and usefulness of a forum is to share problems to find a solution collectively and help others in the future.

you just say 'I changed something and it works'. That won't help anyone else. In fact, it will be a waste of time.

Whenever I post a problem here, if I find the solution myself, I spare some time writing the detailed solution to help others in return for the help I expect from others.

Givers need takers, is just not being a taker all the time.


I perfectly understand it.

The search of the answer was pretty random and included a lot of moving parts and I don't know which ones were the reason, so I cannot write "the detailed solution". 

But in the last two posts I wrote the things I've done based on the recommendations here.

 

Test example design, control initializing routine there, fix timing problems in the design, check on the hardware.

The optional ports used: tx8b10ben, pll0_pd, pll1_pd, txchardispmode, txchardispval.

 

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