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jonr944
Visitor
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Registered: ‎11-29-2018

Simulating Ultrascale+ GTY SDM values with Fracxo

Hi

I have a working GTY transceiver with FRACXO IP project running in a lab, however I am also looking to simulate this framework using ModelSim.

Under simulation, I can see the FracXO logic toggling the SDM data port of the GTY, however the reference clocks never seem to align. The overflow debug outputs eventually assert after a few SDM toggles.

Is there something I'm missing or is this just not supported with the current transceiver (v1.7)?

 

Thanks!

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roym
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Registered: ‎07-30-2007

Simulating Fracxo can be problematic before the Vivado 2020.1.  Both 2019.2 and 2020.1 use the wiz v1.7 so I am unsure of what you are using.  See https://xilinx.sharepoint.com/sites/xkb/SitePages/ArticleViewer.aspx?articleNumber=73537




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jonr944
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Registered: ‎11-29-2018

Hi

 

I am using 2019.2 and wiz 1.7. I have tried 2020.1 and upgraded the IP using the latest wiz and still no joy under simulation.

 

Thanks for the link, however I don't seem to have access to the sharepoint site it would seem...

 

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roym
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Registered: ‎07-30-2007

Sorry, we have a new utility for this.  The link below is better.  Verify the 2020.1 GTY has the fs simulation.  If it doesn't you should be able to make the updates similar to what the AR describes.

https://www.xilinx.com/support/answers/73537.html




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jonr944
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Registered: ‎11-29-2018

Hi

 

I made the updates, however I am still seeing the same issue.

Can anyone confirm that toggling the QPLL SDM values is indeed supported under simulation?

 

Thanks!

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patolsky
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Registered: ‎05-07-2018

@jonr944 

Hi,

How you were able to make design of GTY transceiver with FRACXO IP project running in a lab?
You have connected example design of GTY to FRACXO IP or you made an example design of FRACXO IP?

Thanks,

Patolsky

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ultrascaleaddict
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Registered: ‎11-08-2018

Hello jonr944,

I am starting to use the FRACXO_IP and I was wondering  how to get an optimal simulation. My hypotheses are:

- Vivado 2019.2

- FRACXO_IP v1.0 (the one that comes with Vivado)

- For simulation I am using Modelsim SE-64 2019.4

- RefClk is at 62500 kHz

- TxCLK is at 156.25 MHz

1- My first question is how much do I have to run simulation before getting a lock?

2- So far my simulation is at 80 ms, SDM data is changing, SDM toggle no, the errors_out toggles from 0 to -32 and the volt_o value keeps falling (from 0 to -14587 so far).

 

Maybe I am not waiting enough but while waiting for this simulation, do you have any hint/advice?

 

Thanks in advance.

 

Kind regards, 

 

 

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roym
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Registered: ‎07-30-2007

I don't believe you can have the simulate speedup set for FRACXO.




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