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Visitor vyudovich
Visitor
293 Views
Registered: ‎11-08-2017

Skew timing violation on Transciever clocks

Hi,

I am syntesizing a small design with 10Ghz transciever. 

The clock scheme is this:

GTYE4_CHANNEL.RXOUCLK --> BUFG --> IBUF --> MMCME4_ADV.CLKIN 

from MMCM there are two clocks: 156.25 and 312.5, posedge aligned fed back to the CHANNEL to:

GTYE4_CHANNEL.RXUSRCLK 

and

GTYE4_CHANNEL.RXUSRCLK2

After Implementation phase I get Max SKew violation:

Check TypeCornerLib PinReference PinRequiredActualSlackLocationPin
Max SkewSlowGTYE4_CHANNEL/RXUSRCLK2GTYE4_CHANNEL/RXUSRCLK0.881.57-0.69GTYE4_CHANNEL_X1Y51serdes_wrap/serdes_10g/example_wrapper_inst/serdes_10g_inst/inst/gen_gtwizard_gtye4_top.serdes_10g_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[36].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/RXUSRCLK2

 

Would appriciate inputs and ideas why that is happenign and how to resolve.

Thanks,

Vladimir.

skew.JPG
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2 Replies
Moderator
Moderator
280 Views
Registered: ‎07-30-2007

Re: Skew timing violation on Transciever clocks

The MMCM does not have tight enough timing constraints to drive the USRCLK inputs of the transceivers.  The preferred way to create the clocks is to drive 2 BUFG_GT's which have the ability to do the /2 function.  This will keep the timing skew within the limits on this device.  See page 110 of UG578.




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Xilinx Employee
Xilinx Employee
249 Views
Registered: ‎08-07-2007

Re: Skew timing violation on Transciever clocks

hi @vyudovich 

 

MMCM is not recommanded.

Please follow this article.

https://www.xilinx.com/support/answers/64047.html

 

Thanks,

Boris

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