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Registered: ‎05-30-2017

Spartan 6 3G-SDI RX problem


I'm working with Spartan-6 XC6SLX150T and ISE 14. We made a project for our PCB to receive HD-SDI and it works very well. Then we modified it to receive 3G-SDI and there are a lot of errors in the front end part of reception and I can observe them looking at crc_err outputs of module triple_sdi_rx_s6gtp. I don't see these errors only if I generate a 3g test pattern in the same fpga I send this pattern on an SDI output and than I connect this output to SDI input. So I think that the problem is that the 3g receiver don't correctly recover the clock of 3g sdi input if it has not exactly the same clock of my board. Could someone help me?

Edit: I'm using elastic buffer. Maybe I should bypass elastic buffer and use phase alignament? In which cases one is suggested and in which it is suggested the other one? 

Thank you very much.

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Registered: ‎07-30-2007

Re: Spartan 6 3G-SDI RX problem

When you say you modified it to handle 3G-SDI what did you do?  You should have made a whole new design.  The 3G SDI should double the line rate of the initial design and that might require different PLL attributes that you might not have if you didn't start fresh.

I'm sure the elastic buffer is not the problem.  You normally don't bypass the buffer unless it is required.


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