cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
kondo-akira
Visitor
Visitor
400 Views
Registered: ‎08-24-2018

Spartan-6, AR#35237, about the solution and the cause

Jump to solution

Hi

 

At AR#35237 (https://www.xilinx.com/support/answers/35237.html).

LX150Tand LX75T -FG(G)676: Avoid Pins and additional guidelines

> To avoid excess impact to performance to the GTP Transceivers, certain pins should not be used for toggling I/O.

> The following ranges define a rectangle of pins that should be avoided.

> GCLK pins can still be used, but should be weighted appropriately when calculating the maximum usable number of I/O per the table below.

 

[Question]

What does the meaning of "still" at "GCLK pins can still be used"?

Also, are there any usage conditions other than the guidelines?

I'm wondering if there are other hidden risks from the "still" description.

 

Best regard.

Tags (2)
0 Kudos
1 Solution

Accepted Solutions
karnanl
Xilinx Employee
Xilinx Employee
376 Views
Registered: ‎03-30-2016

Hello @kondo-akira 

The take-away from this answer record is to limit usage of SelectIO pins from bank 0 and bank 2 as little as possible, to minimize SSO affect on GTP pins.
I think the answer record is very clear that you can use GCLK pins on your device, even if GCLK pins are in these area :
   Forb_area.jpg

But please do calculate the points for all of your pins (including GCLK pins) and ensure that total point for banks 0 and bank 2 points are below 80 points.

Regards
Leo


------------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our
Versal Blogs

------------------------------------------------------------------------------------------------

View solution in original post

1 Reply
karnanl
Xilinx Employee
Xilinx Employee
377 Views
Registered: ‎03-30-2016

Hello @kondo-akira 

The take-away from this answer record is to limit usage of SelectIO pins from bank 0 and bank 2 as little as possible, to minimize SSO affect on GTP pins.
I think the answer record is very clear that you can use GCLK pins on your device, even if GCLK pins are in these area :
   Forb_area.jpg

But please do calculate the points for all of your pins (including GCLK pins) and ensure that total point for banks 0 and bank 2 points are below 80 points.

Regards
Leo


------------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our
Versal Blogs

------------------------------------------------------------------------------------------------

View solution in original post