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Visitor
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Registered: ‎04-24-2020

Synchronizing MMCM frequency synthesized clocks between Artix-7 based systems connected by GTP transceiver

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My question is in regards to synchronizing clocks between systems using GTP transceivers and possibly MMCMs.

I'm working on an audio project which utilizes Artix-7 GTP transceivers. There will be one master controller system which generates packets which are sent on the GTP link using SDI type hardware, but the bit stream is a custom 8b/10b encoded stream.  We are currently using a 148.5 MHz oscillator connected to the GTP REFCLK pins to generate a 2.970 Gbps rate.  Connected slave devices will be recording or playing back audio to/from the GTP link.  For this purpose it is critical that all systems are synchronous in regards to the audio streams, so that no buffers over/underflow and it is also necessary that the audio subsystems operate at typical audio sample rates, such as 48 KHz, 96 KHz, and 192 KHz.

The 148.5 MHz oscillator was chosen because it is a typical value used for SDI line rates.  However, the line rate is flexible for this application, so long as the 3G link bandwidth is maximized, and a different oscillator could potentially be used.  The first part of my question is in regards to using an MMCM to synthesize a more friendly audio rate, such as 49.152 MHz (256 x 192 KHz) across all systems.  The master system will be the clocking source for all other connected systems which will use clock recovery on the GTP link for its own clocking.  What I have been unable to determine is the synchronous or asynchronous nature of MMCM subsystems.  If independent MMCMs are utilized on multiple systems, is there any way to make them synchronous if they are using the recovered clock from the GTP link?  Interestingly the 148.5 MHz USRCLK output of the GTP transceiver divides down close to 49.152 MHz by an integer multiple of 3 (actual is 49.5 MHz). However, the Clocking Wizard in Vivado results in strange default values of CLKFBOUT_MULT_F of 6.75 and a Divide of 20.25.  This seems strange, since these should be integer multiple frequencies.

Another potential option would be to choose a different GTP REFCLK oscillator frequency (possibly a custom one), which is more friendly to audio rates.

Any tips on how to achieve such a multi-system synchronous clocking infrastructure would be much appreciated.

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @ElementGreen 
# Perhaps adding a simple picture would make your question more clear.


Please see a picture below:
System_A_B_are_sync.jpg

"A" and "B" are synchronized since rxoutclk is a recovered-clock from GTP RX serial input signal.


Please notice on the picture above that MMCM clock output is 49.5MHz.
Unfortunately, Artix-7 MMCM cannot generate a clock with a precise 49.152MHz from 148.5 MHz input clock. ( Something near 49.152MHz is possible. i.e 49.153.. 48.158.. etc). Please play with the clock wizard to check whether the clock output is suitable for your system.

If you need a precise 49.152MHz MMCM output, you need to use OSC with different clock frequency. (For example 49.152 x2 , or 49.152 x3 MHz). So, your understanding is correct.
Please leave CLKFBOUT_MULT_F/DIVIDE_CLKDIV setting as a default value.

Hope this helps

Kind Regards
Leo

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Xilinx Employee
Xilinx Employee
274 Views
Registered: ‎03-30-2016

Hello @ElementGreen 
# Perhaps adding a simple picture would make your question more clear.


Please see a picture below:
System_A_B_are_sync.jpg

"A" and "B" are synchronized since rxoutclk is a recovered-clock from GTP RX serial input signal.


Please notice on the picture above that MMCM clock output is 49.5MHz.
Unfortunately, Artix-7 MMCM cannot generate a clock with a precise 49.152MHz from 148.5 MHz input clock. ( Something near 49.152MHz is possible. i.e 49.153.. 48.158.. etc). Please play with the clock wizard to check whether the clock output is suitable for your system.

If you need a precise 49.152MHz MMCM output, you need to use OSC with different clock frequency. (For example 49.152 x2 , or 49.152 x3 MHz). So, your understanding is correct.
Please leave CLKFBOUT_MULT_F/DIVIDE_CLKDIV setting as a default value.

Hope this helps

Kind Regards
Leo

View solution in original post

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Visitor
Visitor
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Registered: ‎04-24-2020

Thank you for the very concise and helpful answer!  The diagram you posted does indeed match the system architecture I was describing.  It sounds like what you are saying is that using the MMCM will result in the output being synchronous with the input.  I was not sure if this was the case or if it might even be true in some cases and not others (such as integer only multiply/divide, etc).  I did indeed manage to get pretty close to 49.152 MHz, but was concerned that strange fractional multiply or divide factors would result in something asynchronous between systems.  There will ultimately be several slave systems with a single master, with a daisy chain link connection between them, and all of their clocks need to be synchronous.  This seems to be possible provided the same MMCM configuration is used across all of them.

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