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Visitor
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Registered: ‎11-04-2019

TXOUTCLK driving RXUSRCLK with Buffer Bypassed enabled

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Hi,

I'm currently working in a project using a GTP transceiver Serie 7. I'm using the same oscillator to drive TX and RX channels, so, TXOUTCLK is connected to the RXUSRCLK port. I've also activated the buffer bypassed option. And as I read on the user guide, when the buffer is bypassed in the Single-Lane Auto Mode, the recovered clock from CDR is used to drive RXOUTCLK and then this is used to run RXUSRCLK. Also says that the RX delay alignment continues to adjust RXUSRCLK to compensate for temperature and voltage variations. So my question is, how this can happen if the RXUSRCLK it is not drived by the RXOUTCLK in my case? RXOUTCLK it is not used, so I don't understand the mechanism of RXUSRCLK compesation.

If you know something about this, please let me know.

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Moderator
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Registered: ‎07-30-2007

That's is right.  Only if the far end transmitter shared the same refclk would there be an opportunity to bypass both the buffers as I described earlier.  The clocking setup is pretty specific and is described in more detail in the RX buffer bypass section.




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Guide
Guide
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Registered: ‎01-23-2009

I'm using the same oscillator to drive TX and RX channels

Do you mean that the RX and TX channels on this device use the same oscillator, or the same oscillator is used in both this device and the link partner (the device driving/receiving the other end of these links)?

If the link partner is using its own oscillator, then what you are describing won't work. The TX on the link partner is sending data at a rate that is always slightly different than the rate of the local oscillator. There are two ways to compensate for that

  • use RXRECCLK (the recovered clock) on RXOUTCLK to clock the logic receiving the data on the RX channel (including RXUSRCLK)
  • use "clock correction" using the elastic buffer and a known protocol (i.e. 8b10b) to insert or remove IDLE characters between packets to match the clock rates

What you are describing, using TXOUTCLK to drive RXUSRCLK and not using clock correction will not work; you will periodically end up with either dropped or duplicated samples...

If the link partner is sharing the same oscillator as the FPGA then this fundamental rate mismatch does not exist; and systems can be designed that use neither of the above mechanisms....

so, TXOUTCLK is connected to the RXUSRCLK port

Just because the TX and RX channels in the FPGA use the same REFCLK does not mean that you have to drive the RXUSRCLK with the TXOUTCLK - you can always use the RXOUTCLK. With "clock correction" enabled (or if the link partner shares the same reference clock), there are some cases where you can drive RXUSRCLK with TXOUTCLK, but you never have to.

Avrum

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Visitor
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Registered: ‎11-04-2019

I'm sorry, I didn't explain very well my setup. Just for testing purposals I have connected the TX an RX channels of the same device, I mean, the FPGA is sending itself the data. So, I'm using the same oscilator to drive both channels of the same GTP module. And as the user guide mentions, you can use the TXOUTCLK to drive TXUSRCLK and RXUSRCLK. So, in this case, how does the buffer bypassed and phase alignment work? Regarding all I've mentioned in the previous post.

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Moderator
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Registered: ‎07-30-2007

You can't drive the RXUSRCLK with the TXOUTCLK in all cases.  Bypassing the RXBUFFER sets conditions on the clocking that aren't met using the TXOUTCLK.  Specifically on page 242 of UG476, "The RX elastic buffer can be bypassed if the RX recovered clock is used to source RXUSRCLK and RXUSRCLK2".




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Registered: ‎11-04-2019

I'm using the GTP transceiver serie 7. In the user guide (UG482) on page 214 says the next: 

If the channel is configured so the same oscillator drives the reference clock for the transmitter
and the receiver, TXOUTCLK can be used to drive RXUSRCLK and RXUSRCLK2 in the
same way that they are used to drive TXUSRCLK and TXUSRCLK2. When clock correction
is turned off or the RX buffer is bypassed, RX phase alignment must be used to align the serial
clock and the parallel clocks.

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Registered: ‎07-30-2007

This is a complex area and it could probably have been written more clearly. By transmitter in this context they are talking about the far end transmitter meaning the TXOUTCLK will be synchronous to the rx recovered clock. If you are using clock correction you can drive the RXUSRCLK's with the TXOUTCLK whether the far end is synchronous or not.  If the txoutclk is synchronous to the recovered clock, clock correction is not needed.

If the far end is synchronous, which isn't usually the case, it is possible to bypass both the TX and RX buffers and use the TX as the master channel.  This is an advanced use case and is not recommended if it is not a strict requirement of your design.  The channel driving the TXOUTCLK will do the master alignment then the rest of the tx lanes will do a slave alignment to that master clock (as normal).  All of the rx channels do the slave alignment to that tx master channel clock as well.   This design is a bit less robust than a buffered design in my experience.




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Registered: ‎11-04-2019

I think I understand now. Just to be sure and to summarize, if I have both TX and RX in the same device and in the same GTPE2_CHANNEL and they are both drived by the same REFCLK and buffer is bypassed, I must not use TXOUTCLK to drive RXUSRCLK. The clock signal from the CDR will drive RXUSRCLK, not TXOUTCLK. Am I right?

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Visitor
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Registered: ‎11-04-2019
I mean, the clock signal from CDR will drive RXOUTCLK and finally RXOUTCLK will drive RXUSRCLK
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Moderator
Moderator
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Registered: ‎07-30-2007

That's is right.  Only if the far end transmitter shared the same refclk would there be an opportunity to bypass both the buffers as I described earlier.  The clocking setup is pretty specific and is described in more detail in the RX buffer bypass section.




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Visitor
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Registered: ‎11-04-2019
Thank you very much!
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