11-02-2018 03:28 AM
I need a GTH PHY block for XCZU7EV device. According to PG239-PCIe-PHY, I have generated a GTH PHY block for XCZU9EG device and tried upgrading the IP for xczu7ev and failed. I moved all the RTL source files of the IP into my new project and tried synthesising the same. Synthesis seems fine, however, the post-synthesis timing report shows the TXOUTCLK frequency as double of the required one. Following is the IP configurations;
-Line rate: 5 (Gen2)
-Reference clock frequency: 100 MHz
-PHY core clock frequency: 250 MHz
-PHY user clock frequency: 125 MHz
following is the snapshot of timing summary,
As you can see, all the output frequencies are double than expected.
I'm new to the PHY and transceiver things and appreciate if anyone can guide me to get this GTH PHY implemented in the right way. Thank you!
11-05-2018 01:38 AM
I'm afraid ZU7EV is not supported by this IP as of now.
Please refer to PG239 page.4 for the supported devices list.
For ZU7EV, you can use PCIe Intergrated block IP if possible.
The IP currently can be generated for the
• UltraScale+: ZU9EG (GTH), VU3P (GTY), and
• UltraScale: KU040 (GTH), KU115(GTH),
VU440(GTH), and VU440 ES2(GTH).
11-05-2018 01:59 AM
The IP cannot be generated for ZU7EV however, as per PG239 the GTH PHY can be generated for ZU9EG(for ultrascale+ GTH) and can be migrated to a device which has the matching transceiver type. So I hope migration should be possible for ZU7EV. Vivado doesn't support migration of this IP hence I used all the IP generated sourced files in my project. The following discussion clarifies the same too,
However, I could see frequency mismatch of TXOUT clock at the post-synthesis timing report.
And for your suggestion, I don't need the PCIe integrated block since I'm using Synopsys PCIe controller and need to integrate it with Xilinx GTH PHY. My doubt here is using the IP generated RTL files is enough for the implementation or do any steps/methods available to successfully generate/port this GTH PHY?.
03-21-2019 02:53 AM
Sorry for the late reply, forgot to close this thread as the issue was already resolved.
By default, QPLL is selected in the IP flow. Changing this to CPLL resolved the issue and the PHY was running fine at Gen2 in hardware and the output clocks are as expected.