04-22-2019 08:43 PM
Hi,I am using the Kintex 7 GTX to make a SATA3.0 PHY layer,I have to change the line rate for the compability with the SATA2.0 and SATA1.0,so I make a DRP write to the TXOUT_DIV/RXOUT_DIV,but I think the TXOUTCLK(which is my txusrclk2/rxusrclk2)should be changed with the line rate too,so I choose the TXOUTCLKSEL=3'010 connecting the TXOUTCLK with the TXPMACLK(which is the divided clk from the PLL and can be changed with the line rate),but when I choose this on the PAGE2 in the VIVADO IDE,I found the txoutclk is missing,the PLLOUTCLK is still stable,I am very confused.
so should I set the TXOUTCLKSEL=3'010 when changing the line rate?and why the TXOUTCLK is missing?
this is my project(which is the exmple project of GTX)
thanks a lot!
04-22-2019 11:21 PM
Just giving some hints.
1. Please confirm that all input clocks are stable, before you start initialization.
Please confirm that RESETDONE is asserted, when you are accessing DRP I/F.
2. If those does not solve your issue, Could you please check my post on this ?
( Your issue seems very similar )
Please see (3)
(a) Could you please set your TXCLKOUT_BUFG_INST (bufg) disable at default setting (after configuration)
(b) Enable your bufg, only after you can ensure that TXOUTCLK is stable.
( for example implement a counter using TXOUTCLK, wait 1us, then enable your bufg )
Thanks & regards
04-22-2019 11:30 PM
thanks you very much ,I have found the reason of my question,the TXOUTCLK works now,but if I want to change the line rate,should I change the txusrclk2/rxusrclk2 too?if so,I have to set the TXOUTCLK_SEL=3'010.
thanks a lot
04-23-2019 12:10 AM
Yes, if you change the line-rate, you have to change the frequency of txusrclk2/rxusrclk2 too. (Please see UG476 Chapter 3,4 for the USRCLK/USRCLK2 calculation formula). I can see that you already set TXOUTCLK_SEL=3'010 in your design.
Thanks & regards
04-23-2019 12:30 AM
thank you very much karnanl! you help me a lot!
I have change the TXOUT_DIV to 3'b010 and set the TXRATE and the RXRATE to change the line rate,but the RXRATEDONE and the TXRATEDONE is not drived to 1,this is my simulation picture,should I pull the TXRATE and the RXRATE up after the RXRESETDONE and the TXRESETDONE is high? and according to the ug476,the TRANS_TIME_RATE attributes which indicates the time between TXRATE change and the TXRATEDONE change is set to the 8'h0E,so it means 14us or the 14ms?I guess maybe the simulation time is not enough.And is there any reference code for the TXRATE/RXRATE ports?I just pull these two ports to the 2/3 constantly after I set the TXRATE/RXRATE in a rise-edge of the rxusrclk2(which is same as the txusrclk2),is there any timing suquence required for the TXRATE/RXRATE.
thank you so much!!!please help me.
04-25-2019 03:09 AM
Hello Junnit @junnit
1. You should only change TXRATE/RXRATE value, after you can confirm TX/RXRESETDONE=1 (=means GTX is initialized and ready to use).
2. I believe you can change the line-rate by changing TXRATE/RXRATE value.
TXRATEDONE/RXRATEDONE is asserted if the changing process is completed.
3. You do not have to change TXOUT_DIV setting manually. Changing TXRATE is sufficient.
(Please see Table 3-25 explanation in UG476)
4. You should not modify TRANS_TIME_RATE parameters. This parameter is a Reserved parameter, means you have to use the value generated by GUI.
Thanks & regards