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Visitor junnit
Visitor
209 Views
Registered: ‎05-10-2018

TXOUTCLK stoped after reconfiguration

Hi xilinx employees,

I am using the DRP to write the TXOUT_DIV/RXOUT_DIV to change the line rate for the sata3.0 phy layer,I have succeeded made three changes,the line rate is 6gbps/3gbps/1.5gbps,but when I want to change the line rate again,the usrclk2 which is my txoutclk becomes 'X', I have searched the fommunity forums to solve my problem,I have found this https://forums.xilinx.com/t5/Serial-Transceivers/TXOUTCLK-output-stop-after-reconfguration/td-p/888199, I want to use the (3) method in picture 1,but  I start my project from the GTX example project,so I can't change the BUFG as you can see in picture 2, so the only way I can do is to use the latest vivado version? here is my function simulation result,the TXRESETDONE and the RXRESETDONE are 1 when I do the DRP writing.

thanks for helping me!

捕9.PNG捕1.PNG捕2.PNG捕获.PNG噗1 (1).PNG

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Visitor junnit
Visitor
208 Views
Registered: ‎05-10-2018

Re: TXOUTCLK stoped after reconfiguration

my viavdo version is 2017.2...... 

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Visitor junnit
Visitor
175 Views
Registered: ‎05-10-2018

Re: TXOUTCLK stoped after reconfiguration

it will be good if xilinx employee can give me a solution.

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Xilinx Employee
Xilinx Employee
162 Views
Registered: ‎08-07-2007

Re: TXOUTCLK stoped after reconfiguration

hi @junnit 

 

before writing to DRP, please don't forget to read it first.

You only change the bits that needs to be changed and leave all remaining bits untouched.

here is correct flow for rate change:

 

read DRP --- modify the bits required --- write DRP

 

Thanks,

Boris

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Visitor junnit
Visitor
158 Views
Registered: ‎05-10-2018

Re: TXOUTCLK stoped after reconfiguration

Hi,borisq:

I have change the line rate from 6gbps to 3gbps,1.5gbps,I just write the datain(other bits are set to 0)corresponding to the TXOUT_DIV/RXOUT_DIV,it works fine,are you sure the problem is this?

thanks

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Xilinx Employee
Xilinx Employee
151 Views
Registered: ‎08-07-2007

Re: TXOUTCLK stoped after reconfiguration

hi @junnit 

 

I think you need to take care of 'other bits' during the rate change.

You can write all 0s to 'other bits' if you are sure 'other bits' should be all 0s.

 

Thanks,

Boris

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Visitor junnit
Visitor
140 Views
Registered: ‎05-10-2018

Re: TXOUTCLK stoped after reconfiguration

Hi @borisq 

I have changed my design to the read-modify-write method,but the problem is still here,the rxusrclk2(txoutclk)has become 'X'after I try to write the TXOUT_DIV/RXOUT_DIV from 4 to 1,I can't find any clues about this,as you can see in the picture I use the read-modify-write method to change the TXOUTD_DIV and the RXOUT_DIV,after every DRP,I have pull the soft_reset_i to '1' to reset the whole GTX,I just want to write the DIV 1/2/4 and 1/2/4........ 

my vivado version is 2018.1,Ijust want to use the GTX for the phy layer of the SATA3.0.

please give me a hand,thanks a lot!

捕获.PNG捕获1.PNG捕获2.PNG捕获3.PNG

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Xilinx Employee
Xilinx Employee
113 Views
Registered: ‎08-07-2007

Re: TXOUTCLK stoped after reconfiguration

hi @junnit 

 

You are using QPLL, right? did you observe QPLLOUTCLK? is it still OK?

if so, put all signals of GT_CHANNEL signals in the waveform and see if there is something wrong, especially on the inputs.

all inputs must be connected. inputs cannot be floating.

 

Thanks,

Boris

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