cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
4,555 Views
Registered: ‎04-08-2009

Testing the SFP module ML605

Jump to solution

Hello i am using a proprietary protocol for fiber.

 

I wanted to test the SFP module with a simple design, which loops the incoming logic levels back to the output.

 

Therefore i wrote a very simple module:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top_test is
    Port ( Input : in  STD_LOGIC;
			  Input_n : in  STD_LOGIC;
           Output : out  STD_LOGIC;
			  Output_n : out  STD_LOGIC;
			  Disable_TX : in STD_Logic;
			  SFP_LOS : out STD_logic
			  );
			        -- 125MHz clock output from transceiver
    
end top_test;

architecture Behavioral of top_test is

signal shortcut : std_logic;

   
 
begin

 
IBUFDS_inst : IBUFDS
   generic map (
      DIFF_TERM => FALSE, -- Differential Termination 
      IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
      IOSTANDARD => "DEFAULT")
   port map (
      O => shortcut,  -- Buffer output
      I => Input,  -- Diff_p buffer input (connect directly to top-level port)
      IB => Input_n -- Diff_n buffer input (connect directly to top-level port)
   );


   
   OBUFDS_inst : OBUFDS
   generic map (
      IOSTANDARD => "DEFAULT")
   port map (
      O => Output,     -- Diff_p output (connect directly to top-level port)
      OB => Output_n,   -- Diff_n output (connect directly to top-level port)
      I => shortcut -- Buffer input 
   );
   
	
	

end Behavioral;

 And set the ports in the UCF:

 

###############
##SFP Module
###############
INST "Input" LOC = "E3";    
INST "Input_n" LOC = "E4";
INST "Output" LOC = "C3";
INST "Output_n" LOC = "C4";

 But i get the following error during mapping:

 

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOB component because the site type selected is not compatible. 

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOB was chosen because the IO contains symbols and/or properties consistent
   with input, output, or bi-directional usage and contains no other symbols or
   properties that require a more specific IO component type. Please double
   check that the types of logic elements and all of their relevant properties
   and configuration options are compatible with the physical site type of the
   constraint.

   Summary:
   Symbols involved:
   	PAD symbol "Input" (Pad Signal = Input)
   	DIFFAMP symbol "IBUFDS_inst/IBUFDS" (Output Signal = shortcut)
   Component type involved: IOB
   Site Location involved: E3
   Site Type involved: IPAD

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOBS component because the site type selected is not compatible. 

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOBS was chosen because the IO contains symbols and/or properties consistent
   with differential slave usage. Please double check that the types of logic
   elements and all of their relevant properties and configuration options are
   compatible with the physical site type of the constraint.

   Summary:
   Symbols involved:
   	PAD symbol "Output_n" (Pad Signal = Output_n)
   	SlaveBuffer symbol "OBUFDS_inst/SLAVEBUF.DIFFOUT" (Output Signal = Output_n)
   Component type involved: IOBS
   Site Location involved: C4
   Site Type involved: OPAD

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOBM component because the site type selected is not compatible. 

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOBM was chosen because the IO contains symbols and/or properties consistent
   with differential master usage. Please double check that the types of logic
   elements and all of their relevant properties and configuration options are
   compatible with the physical site type of the constraint.

   Summary:
   Symbols involved:
   	PAD symbol "Output" (Pad Signal = Output)
   	BUFINV symbol "OBUFDS_inst/OBUFDS" (Output Signal = Output)
   Component type involved: IOBM
   Site Location involved: C3
   Site Type involved: OPAD

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOB component because the site type selected is not compatible. 

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOB was chosen because the IO contains symbols and/or properties consistent
   with input, output, or bi-directional usage and contains no other symbols or
   properties that require a more specific IO component type. Please double
   check that the types of logic elements and all of their relevant properties
   and configuration options are compatible with the physical site type of the
   constraint.

   Summary:
   Symbols involved:
   	PAD symbol "Input_n" (Pad Signal = Input_n)
   	SlaveBuffer symbol "IBUFDS_inst/SLAVEBUF.DIFFIN" (Output Signal =
   IBUFDS_inst/SLAVEBUF.DIFFIN)
   Component type involved: IOB
   Site Location involved: E4
   Site Type involved: IPAD

 Do i have to change any description in the ucf?

 

 

 

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
5,409 Views
Registered: ‎08-13-2007

Re: Testing the SFP module ML605

Jump to solution

The transceiver (GTX MGT in this case) pins are special. You can't treat them like normal SelectIO, e.g. infer IBUF -> fabric loopback -> OBUF.

These pins directly connect to the GTX, are dedicated function, and IO standards, etc.

 

While you could make a fabric based loopback by instantiating the GTX (see the user guide or Arch Wiz for example interfacing code), probably a far easier solution is to use the IBERT core and then configure it via the IBERT Analyzer to be in far-end loopback. That solution will handle the GTX, JTAG connectivity via the BSCAN (ICON), DRP interface for transceiver configuration, etc. That's a much easier way to get there for a quick loopback design.

 

http://www.xilinx.com/support/documentation/dt_chipscopepro_chipscope14-2.htm
 http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/chipscope_pro_sw_cores_ug029.pdf
 http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/ug811_ChipScopeUsingIBERTwithAnalyzer.pdf (ChipScope Pro Tutorial: Using an IBERT Core with ChipScope Pro Analyzer)

 

bt

View solution in original post

0 Kudos
3 Replies
Highlighted
Xilinx Employee
Xilinx Employee
5,410 Views
Registered: ‎08-13-2007

Re: Testing the SFP module ML605

Jump to solution

The transceiver (GTX MGT in this case) pins are special. You can't treat them like normal SelectIO, e.g. infer IBUF -> fabric loopback -> OBUF.

These pins directly connect to the GTX, are dedicated function, and IO standards, etc.

 

While you could make a fabric based loopback by instantiating the GTX (see the user guide or Arch Wiz for example interfacing code), probably a far easier solution is to use the IBERT core and then configure it via the IBERT Analyzer to be in far-end loopback. That solution will handle the GTX, JTAG connectivity via the BSCAN (ICON), DRP interface for transceiver configuration, etc. That's a much easier way to get there for a quick loopback design.

 

http://www.xilinx.com/support/documentation/dt_chipscopepro_chipscope14-2.htm
 http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/chipscope_pro_sw_cores_ug029.pdf
 http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/ug811_ChipScopeUsingIBERTwithAnalyzer.pdf (ChipScope Pro Tutorial: Using an IBERT Core with ChipScope Pro Analyzer)

 

bt

View solution in original post

0 Kudos
Highlighted
Explorer
Explorer
4,515 Views
Registered: ‎04-08-2009

Re: Testing the SFP module ML605

Jump to solution

Thank you for the tipps. I will try this. 

0 Kudos
Highlighted
283 Views
Registered: ‎12-19-2019

Re: Testing the SFP module ML605

Jump to solution

Hello, I also want to use SFP on the ML605 board. In the IEE V14.7 environment, I used Ibert. I need to SFP only use the receiver. So I need PAD X0Y17_RX_P and X0Y17_RX_N, but when I look at the HDL Instantion Template, then there is a lot of PAD, not needed to me. I do not know what to do with PADs. How to correctly configure SFP to the receiver?

p.s. I take the CLK on the board from the SMA connectors, the frequency is the same as on the transmitter

Tags (3)
IMG_20191220_100051.jpg
IMG_20191220_100045.jpg
0 Kudos