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pavan_619@
Adventurer
Adventurer
722 Views
Registered: ‎03-13-2019

The question is which signal should be used in JESD204C?

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Hello guys,

When I checked transport layer mapping in JESD204B user guide I found
Start of frame signal is quite useful in transport layer mapping and demapping.

After looking into JESD204C 64/66 line coding I am totally lost.
Therefore no conventional signal start of frame.

Later I found (start of extended multi block signal).

Is this can be considered similar to SOF?

Any help is useful
Thank you

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pavan_619@
Adventurer
Adventurer
496 Views
Registered: ‎03-13-2019

Hello guys, 

I resolved the problem.

It is always better to double check the reference design provided by xilinx.

I used same example design with my modification and it works.

RX data 128 bit can be mapped 256 bit TX data.(By appending zero in my case)

Since there is no SOF signal in JESD204C we can directly map and de-map the data.
Note: We should properly assign tx_tready and soemb signal.

Thank you 


Regards
Pavan

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eschidl
Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi pavan_619@,

yes, that would be the equivalent for the 64b66b encoding setup.

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pavan_619@
Adventurer
Adventurer
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Registered: ‎03-13-2019

Hello @eschidl 

Thank you for clearing the doubt.

But if you consider the that signal (start of extended multi block) it will be little confusing for me to handle that signal

If the example design of JESD204C the mapping and de-mapping of data with respect to start of extended multi block signal is not so clear.

For example, 
If my RX and TX lane config is as follows
RX Config RX data width (128 bits)

L2
K32
M8
F8
S1
NP16


TX config Tx data width (256 bits)

L4
K32
M8
F4
S1
NP16


Here I have to map 128 bits RX data from 2 lanes to 256 bits of TX data for 4 lanes

In this how can i use (start of extended multi block) signal in mapping and de-mapping?

I am missing some understanding here.

Can you guide me?
Thank you

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pavan_619@
Adventurer
Adventurer
497 Views
Registered: ‎03-13-2019

Hello guys, 

I resolved the problem.

It is always better to double check the reference design provided by xilinx.

I used same example design with my modification and it works.

RX data 128 bit can be mapped 256 bit TX data.(By appending zero in my case)

Since there is no SOF signal in JESD204C we can directly map and de-map the data.
Note: We should properly assign tx_tready and soemb signal.

Thank you 


Regards
Pavan

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