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Registered: ‎04-11-2017

There is No output signal at IBUFDS_GTE4 ODIV2 pin.



I found something strange recently using IBUFDS_GTE4.

Device: Zynq UltraScale+ MPSoC




Shown in the figure, I use this way to drive my JESD204 core_clk , which is driven by IBUFDS_GTE4.ODIV2.

And also the core_clk was set as debug core domain in my project.

It succeed when I:

1. Gen the ref_clock for the IBUFDS_GTE4 at the very frist time. And then

2. Power up the Zynq board and programed the bitfile.

3. Read the GT PLL status which is LOCKED.

And I can detect the debug core and the whole system works fine.


It failed when I:

1. Power up the Zynq board and programed the bitfile And then

2. Gen the ref_clock for the IBUFDS_GTE4.

3. Read the GT PLL status which is LOCKED.

Vivado CANNOT detect any debug core and the system don't work.


And I think maybe something went wrong with my IBUFDS_GTE4.

But according to ug576 when REFCLK_HROW_CK_SEL attribute is 2b'00 the ODIV2 works as O, which is setting by default.


Could someone help me with this?


Thanks in advance.


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3 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎10-19-2011

Hi @yashenseu,


the IBUFDS_GTE4 is working. Otherwise the PLL would not lock.

It is just the startup timing that gives you problems.

The debug cores will be detected directly at the end of writing the bitstream and the debug clock needs to be present for that.

If you enable the clock after programming the device the debug cores will not be seen at this point.

Similarly the JESD core and the GTs will start up. They need the clock present.

Does a reset of the IP later bring the system up then?

Don't forget to reply, give kudo and accept as solution
Registered: ‎04-11-2017

I mean, I could not see any debug cores after I refresh my device, which means the clock is not free running or not the right debug file.


According to the pg198. I read the status of REG PLLStatus 0x080, which turns out to be 0x1c(TX and RX reset in progress).

Bits Default Value Description
31:5 Reserved
4 Returns 1 when a transmit reset is in progress.
3 Returns 1 when a receive reset is in progress.
2 Returns 0 when all the CPLLs are locked.
1 Returns 0 when all the QPLLs (7 series) or QPLL0s (UltraScale) are locked.
0 Returns 0 when all the QPLL1s are locked (UltraScale only, always returns 0
for 7 series devices).

Then I reset the JESD-phy via REG 0x420 and REG 0x424 and then read REG PLLStatus 0x080 which turns out to be 0x00 which means that JESDPhy finish the reset progress and CPLL is locked.

But the JESD204 IP core is not working, and refresh the device, the Vivado could not detect any debug cores.

And reset the reset pin of the IP core won't work.

By the way, in Kintex-7 device, my JESD204 design uses a free run clock signal to drive core_clk(glb_clk) leaving the reset pin at low. And it works fine.
Its clocks are enabled after writing the bitstream file.


Here is the share clk code. it's the same as the one in JESD204 IP core example design.


//***********************************Entity Declaration*******************************

module share_clock
  input  wire     refclk_pad_n,
  input  wire     refclk_pad_p,
  output wire     refclk,
  output          coreclk

//*********************************Wire Declarations**********************************
  wire            tied_to_ground_i;
  wire            tied_to_vcc_i;
  wire            refclk_i;
  wire            coreclk_i;

  wire            refclk_buf_i;
  wire            refclk_copy;

  //*********************************** Beginning of Code *******************************

  //  Static signal Assigments
  assign tied_to_ground_i    = 1'b0;
  assign tied_to_vcc_i       = 1'b1;

  IBUFDS_GTE4 ibufds_refclk0
    .O               (refclk_i),
    .ODIV2           (refclk_copy),
    .CEB             (tied_to_ground_i),
    .I               (refclk_pad_p),
    .IB              (refclk_pad_n)

  BUFG_GT refclk_bufg_gt_i
    .I       (refclk_copy),
    .CE      (1'b1),
    .CEMASK  (1'b1),
    .CLR     (1'b0),
    .CLRMASK (1'b1),
    .DIV     (3'b000),
    .O       (refclk_buf_i)

  assign refclk  = refclk_i;
  assign coreclk = refclk_buf_i;

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Xilinx Employee
Xilinx Employee
Registered: ‎10-19-2011

Hi @yashenseu,


is it not possible for you to follow the sequence with which the core is coming up correctly and you see the debug cores?


Your code for clock module looks fine.

But do you by chance have another free running clock in your setup to connect the debug cores to?

Then it would be possible to do some more debug of your failing situation if you have to go that way.


Did you reset the JESD core too when resetting the PHY and initialise the link?


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