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Adventurer
Adventurer
308 Views
Registered: ‎08-15-2018

Transceiver DRP clock unable to be set to maximum value in specification

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I'm receiving the following error:

ERROR: [IP_Flow 19-3488] Validation failed for parameter 'Free-running and DRP clock frequency (MHz)(FREERUN_FREQUENCY)' for IP 'gtwizard_ultrascale_0'. Value '250' is out of the range (3.125,40.5)

The transceiver is setup with a reference clock  of 81MHz, so the maximum of 40.5MHz above is from dividing the current reference clock by two. The specification of the DRP clock is up to 250MHz - why would the GT lane rate dictate the speed of the DRP clock, which is orthogonal to the operation of the GTs?

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Xilinx Employee
Xilinx Employee
285 Views
Registered: ‎06-01-2017

Re: Transceiver DRP clock unable to be set to maximum value in specification

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Hi @bitstreamer 

The wizard shares the same source DRPCLK with freerun clock. The DRPCLK can run up to 250MHz, however, the freerun clock has limitation. See PG182 Table 2-1. https://www.xilinx.com/support/documentation/ip_documentation/gtwizard_ultrascale/v1_7/pg182-gtwizard-ultrascale.pdf.

The freerun clock must comply with the limitation. If you would like to run DRPCLK at a higher frequency, you can modify the RTL such that DRPCLK gets its own clock source, then make sure it does not exceed 250MHz.

image.png

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-01-2017

Re: Transceiver DRP clock unable to be set to maximum value in specification

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Hi @bitstreamer 

The wizard shares the same source DRPCLK with freerun clock. The DRPCLK can run up to 250MHz, however, the freerun clock has limitation. See PG182 Table 2-1. https://www.xilinx.com/support/documentation/ip_documentation/gtwizard_ultrascale/v1_7/pg182-gtwizard-ultrascale.pdf.

The freerun clock must comply with the limitation. If you would like to run DRPCLK at a higher frequency, you can modify the RTL such that DRPCLK gets its own clock source, then make sure it does not exceed 250MHz.

image.png

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Adventurer
Adventurer
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Registered: ‎08-15-2018

Re: Transceiver DRP clock unable to be set to maximum value in specification

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Is there anyway to separate the two clock domains so the DRP can run at the 250MHz rate? Or do I have to instantiate SERDES primitives directly and bypass the wizard?

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-01-2017

Re: Transceiver DRP clock unable to be set to maximum value in specification

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Hi @bitstreamer, the sharing logic resides in the example design so you should be able to modify the RTL (it's not locked inside the IP core). You should always use the wizard to configure/instantiate the GT.

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