cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
612 Views
Registered: ‎03-19-2019

Transceivers Wizard on ZCU102

Jump to solution

Hello everyone,

I'm trying to use transceivers on my ZCU102 board. I used the IBERT IP which worked perfectly and now I want to use the Transceivers Wizard. I have used the exact same configurations but I'm facing all the time the same issue :

WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
INFO: [Labtools 27-1434] Device xczu9 (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'gtwizard_ultrascale_0_vio_0_inst' at location 'uuid_29651C5239AB59FCAAA25225A6767F8B' from probes file, since it cannot be found on the programmed device.

 

I think it's a clock issue but I don't understand it.

My settings are these one :

Capture1.PNGCapture.PNG

With these settings I'm using the SI570 oscillator which is automatically set at 156.25MHz, thus, I don't understand why the clock is not recognized.

Do you have any idea ?

Regards,

Emilie 

 

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
559 Views
Registered: ‎10-19-2011

Re: Transceivers Wizard on ZCU102

Jump to solution

Hi @emilie ,

from you xdc I see that the free running clock is still a separate input, but you wanted to use the reference clock as the free running clock, I guess.

You will need to adjust the example design. Remove hb_gtwiz_reset_clk_frerun_in from the port list and connect it to the ODIV2 output of the IBUFDS_GTE. Then you can also comment out the constraint for the removed port.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post

0 Kudos
13 Replies
Highlighted
Moderator
Moderator
591 Views
Registered: ‎01-10-2019

Re: Transceivers Wizard on ZCU102

Jump to solution

Hi @emilie ,

It look like clock connected to the debug hub is not free running . Can you please check the XDC file and make sure clock are routed correctly .

Thanks,
Rahul Khatri
---------------------------------------------------------------------------------
Please Kudo or Accept as a solution, If this Post helped you.
---------------------------------------------------------------------------------
0 Kudos
Highlighted
Contributor
Contributor
584 Views
Registered: ‎03-19-2019

Re: Transceivers Wizard on ZCU102

Jump to solution

Hello @rkhatri ,

Thank you for your quick answer.

Here my .XDC

# Location constraints for differential reference clock buffers
# Note: the IP core-level XDC constrains the transceiver channel data pin locations
# ----------------------------------------------------------------------------------------------------------------------
set_property package_pin L28 [get_ports mgtrefclk0_x0y2_n]
set_property package_pin L27 [get_ports mgtrefclk0_x0y2_p]


# Clock constraints for clocks provided as inputs to the core
# Note: the IP core-level XDC constrains clocks produced by the core, which drive user clocks via helper blocks
# ----------------------------------------------------------------------------------------------------------------------
create_clock -name clk_freerun -period 6.4 [get_ports hb_gtwiz_reset_clk_freerun_in]
create_clock -name clk_mgtrefclk0_x0y2_p -period 6.4 [get_ports mgtrefclk0_x0y2_p]

 

In ZCU102 Evaluation Board User guide, there is :

Capture3.PNG

L27 and L28 are clocks connected to SI570.

Maybe I'm wrong but it seems to be connected, right ?

Regards,

Emilie

0 Kudos
Highlighted
Adventurer
Adventurer
571 Views
Registered: ‎05-07-2018

Re: Transceivers Wizard on ZCU102

Jump to solution
Hi,
in your GUI, I don't see the selected channel? Are you choose one? and Are you sure about existence of all the clocks? DRP clk, ...
0 Kudos
Highlighted
Explorer
Explorer
570 Views
Registered: ‎03-16-2019

Re: Transceivers Wizard on ZCU102

Jump to solution

you should check your dbg_hubs clock from schematic after implementation. this pin (clock of dbg_hub component) should be connected to the freerun non-stop clock. trace the clock pin to figure out this issue.

I haven't seen your hb_gtwiz_reset_clk_freerun_in assignment. do you assign this to a good input clock ?

what is your ILA/VIO core clock?

----------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution
----------------------------------------------------------------------------

 

 

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
560 Views
Registered: ‎10-19-2011

Re: Transceivers Wizard on ZCU102

Jump to solution

Hi @emilie ,

from you xdc I see that the free running clock is still a separate input, but you wanted to use the reference clock as the free running clock, I guess.

You will need to adjust the example design. Remove hb_gtwiz_reset_clk_frerun_in from the port list and connect it to the ODIV2 output of the IBUFDS_GTE. Then you can also comment out the constraint for the removed port.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post

0 Kudos
Highlighted
Contributor
Contributor
556 Views
Registered: ‎03-19-2019

Re: Transceivers Wizard on ZCU102

Jump to solution

Hello @behnam_2705new ,

I have found these assignements on Internet and I used it thinking they were not important :

# Location constraints for other example design top-level ports
# Note: uncomment the following set_property constraints and replace "<>" with appropriate pin locations for your board
# ----------------------------------------------------------------------------------------------------------------------
set_property package_pin H11 [get_ports hb_gtwiz_reset_clk_freerun_in]
set_property iostandard  LVCMOS18 [get_ports hb_gtwiz_reset_clk_freerun_in]

set_property package_pin K14 [get_ports hb_gtwiz_reset_all_in]
set_property iostandard  LVCMOS18 [get_ports hb_gtwiz_reset_all_in]

set_property package_pin V9 [get_ports link_down_latched_reset_in]
set_property iostandard  LVCMOS18 [get_ports link_down_latched_reset_in]

set_property package_pin AA3 [get_ports link_status_out]
set_property iostandard  LVCMOS18 [get_ports link_status_out]

set_property package_pin AB1 [get_ports link_down_latched_out]
set_property iostandard  LVCMOS18 [get_ports link_down_latched_out]

So, what is hb_gtwiz_reset_clk_freerun_in ? And which kind of pins should it be connected to?

I'm trying to use IBERT.

 

Thank you for your reply,

Best regards,

Emilie

0 Kudos
Highlighted
Explorer
Explorer
542 Views
Registered: ‎03-16-2019

Re: Transceivers Wizard on ZCU102

Jump to solution
hb_gtwiz_reset_clk_freerun_in  is your free run clock that should br connected to your GT freerun clock port
this is important signal.
hb_gtwiz_reset_all_in this signal is your GT reset signals, this signal is very important too.

 I couldn't find H11 and K14 pin in ZCU102, and this seems the main problem. you havent had a free-run clock and your reset signal is always tied to 0.

freerun clock is used by GT transceivers for reset procedure. after you correct this two pins double-checked reset done signal in your GT.

don't hesitate to ask a question, we are here to help our co-workers :)

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

Highlighted
Contributor
Contributor
509 Views
Registered: ‎03-19-2019

Re: Transceivers Wizard on ZCU102

Jump to solution

Thank you @behnam_2705new , I understand better know.

 

Hello @eschidl ,why do I have to connect hb_gtwiz_reset_clk_frerun_in to the ODIV2 output of the IBUFDS_GTE ? And what about this signal hb_gtwiz_reset_all_in

 

Thank you all for your answers,

Regards,

Emilie

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
494 Views
Registered: ‎10-19-2011

Re: Transceivers Wizard on ZCU102

Jump to solution

Hi @emilie ,

the ODIV2 output is the port to bring the reference clock into fabric. And if you want to use the reference clock as the free running clock that would be the way to connect it.

For the hb_gtwiz_reset_all_in, you might want to initialise your design now and then, e.g. when your input signal changes or so. The transceiver does an initial reset after configuration. But for everything after you would need to provide the control yourself. For test purposes you could put it on a push button of ZCU102. Have a look at page 79 and following of UG1182 for this.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
Highlighted
Contributor
Contributor
484 Views
Registered: ‎03-19-2019

Re: Transceivers Wizard on ZCU102

Jump to solution

Hi  @eschidl

It is clear now. Thank you !

A last question, I'm trying to assign the correct free running clock but I'm dealing with this issue :

[DRC REQP-1930] IBUFDS_GTE4_ODIV2_may_only_drive_BUFG_GT: The IBUFDS_GTE4 IBUFDS_GTE4_MGTREFCLK0_X0Y2_INST ODIV2 pin may only be connected to a BUFG_GT or BUFG_GT_SYNC component. The IBUFDS_GTE4 ODIV2 pin cannot drive bufg_clk_freerun_inst.

Regards,

Emilie

0 Kudos
Highlighted
Explorer
Explorer
478 Views
Registered: ‎03-16-2019

Re: Transceivers Wizard on ZCU102

Jump to solution

Odiv2 must be connected to bufg_GT

For freerun clk, take a simple clock and use. Its not force to use mgtref clk as a freerun.

 

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
471 Views
Registered: ‎10-19-2011

Re: Transceivers Wizard on ZCU102

Jump to solution

Hi @emilie ,

okay, I forgot about that. In the original design the incoming clock is supposed to come in on a normal pin where it is then driven by a BUFG into the design.

Using the IBUFDS_GTE you would need to change that primitive from BUFG into BUFG_GT (should there also be another input buffer on the port, you can remove that).

 

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
Highlighted
Contributor
Contributor
460 Views
Registered: ‎03-19-2019

Re: Transceivers Wizard on ZCU102

Jump to solution

It works!

Thank you for helping me!

Regards,

Emilie

0 Kudos