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davelinney
Visitor
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Registered: ‎03-08-2018

Trying to use GT Debugger to perform Eye Scan

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Have built the IBERT design for our hardware (not a dev-card).

Have selected and analysed the post-synth checkpoint file

Synthesis throws up the following errors (from log file)


****** Vivado v2018.3_AR71898 (64-bit)
**** SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
**** IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source F:/Design/Temp/san_e/run_viv_syn.tcl
# source F:/Design/Temp/san_e/insert_gt_dbg/insert_gt_dbg.tcl
# insert_gt_dbg modify F:/Design/Temp/san_e/san_e_zynq.dcp
Command: open_checkpoint F:/Design/Temp/san_e/insert_gt_dbg/igd_orig.dcp

Starting open_checkpoint Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 253.223 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 338 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2018.3_AR71898
INFO: [Device 21-403] Loading part xc7z035fbg676-2
INFO: [Project 1-570] Preparing netlist for logic optimization
CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'base_zynq_auto_pc_0' instantiated as 'base_zynq_i/ps7_0_axi_periph/m00_couplers/auto_pc' [F:/Design/Kintex/san_e_trial/san_e_zynq.srcs/sources_1/bd/base_zynq/synth/base_zynq.v:1987]
CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'base_zynq_auto_pc_1' instantiated as 'base_zynq_i/ps7_0_axi_periph/s00_couplers/auto_pc' [F:/Design/Kintex/san_e_trial/san_e_zynq.srcs/sources_1/bd/base_zynq/synth/base_zynq.v:2879]
CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'base_zynq_axi_bram_ctrl_0_0' instantiated as 'base_zynq_i/bond_controller' [F:/Design/Kintex/san_e_trial/san_e_zynq.srcs/sources_1/bd/base_zynq/synth/base_zynq.v:345]
CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'base_zynq_axi_epc_0_0' instantiated as 'base_zynq_i/hpi_controller' [F:/Design/Kintex/san_e_trial/san_e_zynq.srcs/sources_1/bd/base_zynq/synth/base_zynq.v:390]
CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'base_zynq_blk_mem_gen_0_0' instantiated as 'base_zynq_i/blk_mem_gen_0' [F:/Design/Kintex/san_e_trial/san_e_zynq.srcs/sources_1/bd/base_zynq/synth/base_zynq.v:337]
CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'base_zynq_bond_controller_0' instantiated as 'base_zynq_i/scratchpad' [F:/Design/Kintex/san_e_trial/san_e_zynq.srcs/sources_1/bd/base_zynq/synth/base_zynq.v:640]
CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'base_zynq_processing_system7_0_0' instantiated as 'base_zynq_i/processing_system7_0' [F:/Design/Kintex/san_e_trial/san_e_zynq.srcs/sources_1/bd/base_zynq/synth/base_zynq.v:426]
CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'base_zynq_rst_ps7_0_50M_0' instantiated as 'base_zynq_i/rst_ps7_0_50M' [F:/Design/Kintex/san_e_trial/san_e_zynq.srcs/sources_1/bd/base_zynq/synth/base_zynq.v:629]
CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'base_zynq_xbar_0' instantiated as 'base_zynq_i/ps7_0_axi_periph/xbar' [F:/Design/Kintex/san_e_trial/san_e_zynq.srcs/sources_1/bd/base_zynq/synth/base_zynq.v:1667]
CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'tmac_2g5_gtp' instantiated as 'san_e/gts_tmac' [F:/Design/Kintex/san_e_trial/san_e_zynq.srcs/sources_1/rtl/san_e_sgmii.v:109]
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 794.887 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 14 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 8 instances
RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 6 instances

INFO: [Project 1-604] Checkpoint was created with Vivado v2018.3_AR71898 (64-bit) build 2405991
open_checkpoint: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 794.887 ; gain = 541.664
dictionaries and insert_gt_dbg.do loaded
generate igd_bd_jtag2axi2drpgpio
Wrote : <Q:\BDpr.srcs\sources_1\bd\igd_bd_jtag2axi2drpgpio\igd_bd_jtag2axi2drpgpio.bd>
run through file list for clock (should be first line with 'y' at the beginning)
can't read "::_igd_aclk_freq_ds_hz": no such variable
while executing
"list CONFIG.FREQ_HZ $::_igd_aclk_freq_ds_hz"
(procedure "igd_create_bd" line 64)
invoked from within
"igd_create_bd"
("modify" arm line 35)
invoked from within
"switch [lindex $args 0] {
analyze -
analyse {
set ::_igd_orig_dcp [lindex $args 1]
# get dir of DCP and chec..."
invoked from within
"if [llength $args] {
switch [lindex $args 0] {
analyze -
analyse {
set ::_igd_orig_dcp [lindex $args 1]
..."
(procedure "insert_gt_dbg" line 4)
invoked from within
"insert_gt_dbg modify F:/Design/Temp/san_e/san_e_zynq.dcp"
(file "F:/Design/Temp/san_e/run_viv_syn.tcl" line 4)
INFO: [Common 17-206] Exiting Vivado at Fri Nov 15 09:09:22 2019...
child process exited abnormally

 

Questions;

Can GT Debugger not handle user RTL code?

Is the real problem the clock related warning?

Have no way of progessing this myself.

Can anyone help?

Dave

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1 Solution

Accepted Solutions
eschidl
Xilinx Employee
Xilinx Employee
564 Views
Registered: ‎10-19-2011

Hi @davelinney ,

some parts of the design and the clock information seems to be missing in the DCP.

Did you write the checkpoint out with the write_checkpoint command or just grabbed the one from synthesis run directory? only the first one would have all information included.

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2 Replies
eschidl
Xilinx Employee
Xilinx Employee
565 Views
Registered: ‎10-19-2011

Hi @davelinney ,

some parts of the design and the clock information seems to be missing in the DCP.

Did you write the checkpoint out with the write_checkpoint command or just grabbed the one from synthesis run directory? only the first one would have all information included.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post

davelinney
Visitor
Visitor
490 Views
Registered: ‎03-08-2018

Many thanks Eschidl

Yes, thats what it was. 

The write-checkpoint option wasn't showing for some reason.  Didn't appear until I'd actually opened the synthed design.

Works a treat now tho.  Still seems a strange notion that the post-synth checkpoint wouldn't be exactly the same thing.

Regards

Dave

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