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Newbie
Newbie
336 Views
Registered: ‎10-08-2007

UG576 Figure 2-29 is wrong

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I was implementing DRP interface for Ultrascale+ GTH and found an error in UG576 Figure 2-29:

DRPWE should not go high for Read operation.

 

Table 2-38:

DRP write enable.
0: Read operation when DRPEN is 1.
1: Write operation when DRPEN is 1.

 

This should be corrected in next version of UG576.

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Xilinx Employee
Xilinx Employee
312 Views
Registered: ‎10-19-2011

Re: UG576 Figure 2-29 is wrong

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Hi @pejdstran ,

thanks for pointing this out.
There exists already a request to update this, so it should be updated in the future.

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Xilinx Employee
Xilinx Employee
313 Views
Registered: ‎10-19-2011

Re: UG576 Figure 2-29 is wrong

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Hi @pejdstran ,

thanks for pointing this out.
There exists already a request to update this, so it should be updated in the future.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post

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