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Explorer
Explorer
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Registered: ‎07-10-2013

US+ GTY Package-limited Linerates

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DS890 (v3.3) indicates on p.8 for Note 3 that the FFVA1156 package limits the maximum linerate to 16.3Gbps.

 

When using parts with such packages, do both the FPGA hardware and Vivado (and/or other tools) properly support setting up oversampling applications, e.g., where the linerate is 14Gbps but the locked-to-reference xcvr is set up to 2x oversample the incoming serial data at 28GHz?

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @chsdkj,

 

while it might be the case that the silicon can go much faster than the package allows, the selection of dies that go into these packages might not reach 28Gbps. They will be specifically selected to go into these packages.

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Mentor
Mentor
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Registered: ‎02-24-2014

The DRC's built into the tools may complain about your 28 GHz sampling rate, but it's easy enough to work around that by using a 14 GHz rate for startup, and then switching the rate to 28 GHz using the dynamic control registers.   You will have to set up all the attributes and control registers yourself..   Oversampling like this is not a standard application.

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Explorer
Explorer
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Registered: ‎07-10-2013

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @chsdkj,

 

while it might be the case that the silicon can go much faster than the package allows, the selection of dies that go into these packages might not reach 28Gbps. They will be specifically selected to go into these packages.

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Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post