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Explorer
Explorer
335 Views
Registered: ‎07-10-2013

US+ GTY RX Lock-to-reference CDR-locked Status in Reset Controller Helper Block

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PG182 (v1.7) illustrates in Fig.3-1 on p.62 the Receiver Reset State Machine of the Reset Controller Helper Block.  The state machine has state ST_RESET_RX_WAIT_CDR.  In a lock-to-reference situation (RXCDRHOLD=1 and RXCDROVRDEN=0 (per UG578 (v1.3), p.216)) is a CDR lock condition indicated (i.e., as it would be for lock-to-data situations), or will the state machine hang up in that state as a result of the CDR not reporting a lock condition?

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Xilinx Employee
Xilinx Employee
311 Views
Registered: ‎08-07-2007

回复: US+ GTY RX Lock-to-reference CDR-locked Status in Reset Controller Helper Block

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hi @chsdkj 

 

The state machine will not hang up in this state if RXCDRLOCK output is not asserted.

there is a watchdog timer which will break the state and the state machine can proceed to the next state although RXCDRLOCK is not asserted.

below is a piece of code in our reset helper block.

 

// Await an indication of CDR stability (either the direct transceiver RXCDRLOCK output, or expiration of the
// specified maximum CDR locking time, whichever occurs first) before removing the RX programmable divider reset
// and proceeding
ST_RESET_RX_WAIT_CDR: begin
if (rxcdrlock_sync || sm_reset_rx_cdr_to_sat) begin
rxprogdivreset_out <= 1'b0;
sm_reset_rx_cdr_to_clr <= 1'b1;
sm_reset_rx <= ST_RESET_RX_WAIT_USERRDY;
end
end

 

Thanks,

Boris

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Xilinx Employee
Xilinx Employee
312 Views
Registered: ‎08-07-2007

回复: US+ GTY RX Lock-to-reference CDR-locked Status in Reset Controller Helper Block

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hi @chsdkj 

 

The state machine will not hang up in this state if RXCDRLOCK output is not asserted.

there is a watchdog timer which will break the state and the state machine can proceed to the next state although RXCDRLOCK is not asserted.

below is a piece of code in our reset helper block.

 

// Await an indication of CDR stability (either the direct transceiver RXCDRLOCK output, or expiration of the
// specified maximum CDR locking time, whichever occurs first) before removing the RX programmable divider reset
// and proceeding
ST_RESET_RX_WAIT_CDR: begin
if (rxcdrlock_sync || sm_reset_rx_cdr_to_sat) begin
rxprogdivreset_out <= 1'b0;
sm_reset_rx_cdr_to_clr <= 1'b1;
sm_reset_rx <= ST_RESET_RX_WAIT_USERRDY;
end
end

 

Thanks,

Boris

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