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Registered: ‎07-10-2013

US/US+ BUFG_GT Functionality

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UG572 (v1.8) p.32-34 describe the BUFG_GT buffer and its CEMASK, CE, CLRMASK and CLR control inputs.  The description is relatively clear that for normal operation, CE should be high and CLR should be low.  The description does not indicate however at what level(s) the CEMASK and CLRMASK mask inputs should be in order to enable the CE and CLR inputs.

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Registered: ‎01-22-2015

Re: US/US+ BUFG_GT Functionality

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@chsdkj 

Here is description from page 34 of the 09Apr18 version of UG572:

The mask pins (CEMASK and CLRMASK) control how a specific, single BUFG_GT responds to the CE/CLR control inputs. When a mask pin is deasserted, its respective control pin has their normal function. When a mask pin is asserted, the respective control pin is ignored, in effect allowing the clock to propagate through (i.e., CE is effectively High and reset is effectively Low).

So, setting both CEMASK and CLRMASK low will enable the CE and CLR pins.

Cheers,
Mark

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426 Views
Registered: ‎01-22-2015

Re: US/US+ BUFG_GT Functionality

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@chsdkj 

Here is description from page 34 of the 09Apr18 version of UG572:

The mask pins (CEMASK and CLRMASK) control how a specific, single BUFG_GT responds to the CE/CLR control inputs. When a mask pin is deasserted, its respective control pin has their normal function. When a mask pin is asserted, the respective control pin is ignored, in effect allowing the clock to propagate through (i.e., CE is effectively High and reset is effectively Low).

So, setting both CEMASK and CLRMASK low will enable the CE and CLR pins.

Cheers,
Mark

View solution in original post

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