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Explorer
Explorer
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Registered: ‎07-10-2013

US/US+ GTH/GTY XCVR SSC RX OUtput Clock Behavior

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Certain serial protocols utilize SSC clocking, often 0..-5000PPM frequency downspread, 30..33KHz modulation frequency.  A 5000PPM change over 15us implies an average change in the datarate of about 1PPM every several nanoseconds.

 

For SSC protocols supported by US/US+ GTH/GTY XCVRs (such as 6Gbps SATA), is RXUSRCLK/RXUSRCLK2 produced by the XCVR "well-behaved", mimicking the behavior of the RX CDR-related circuitry in the XCVR (not to be confused with the RefClk-fed QPLL or CPLL) so that the frequency of RXUSRCLK/RXUSRCLK2 would likewise change smoothly about 1PPM every several nanoseconds, or can the RX output clocks possibly behave in some less-expected non-continuous (jumpy/discrete) manner (which could still be quite satisfactory however for the purpose of clocking the RX data into a downstream FIFO or other fabric logic)?

 

Note that clock jitter issues are not the concern here.

 

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Xilinx Employee
Xilinx Employee
1,527 Views
Registered: ‎11-29-2007

hello,

to answer your question we should look in the Phase Interpolator: the minimum phase jump is 1UI/128

kind regards,

GG

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Xilinx Employee
Xilinx Employee
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Registered: ‎11-29-2007

hello,

this is true not only for SSC: the recovered clock coming from a PI-based CDR is affected by DJ.

With a SSC you will see small phase jumps in the same direction; the direction will change with the SSC frequency, i.e. 33KHz (*).

The SSC frequency is very low and will not be filtered by the CDR. The recovered clock jumps are not "unexpected" , they are due to the CDR tracking activity, but due to the uncorrelated phase of TX and RX clock domains you will see non constant phase corrections.

This is still OK to read from the RXBUFFER.

hope it answers to your question

-gg

 

 

(*) if TX and RX oscillators ppm difference without SSC is less than the max SSC ppm modulation - this is the common case.

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Explorer
Explorer
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Registered: ‎07-10-2013

@gguasti,

 

Understood.  So, for the SSC case, where an ideal smoothly-changing RX clock would be expected to show a frequency change of 1PPM every several nanoseconds, what would the magnitude of the discrete phase corrections an actual RX clock would exhibit instead roughly be expected to be?

 

 

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Xilinx Employee
Xilinx Employee
1,528 Views
Registered: ‎11-29-2007

hello,

to answer your question we should look in the Phase Interpolator: the minimum phase jump is 1UI/128

kind regards,

GG

View solution in original post

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