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Explorer
Explorer
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Registered: ‎07-10-2013

US+ XCVR RX CDR Lock-To-Reference Data-sampling Timing Adjustment

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The CDR of a GTY xcvr (such as in the XCKU3PP-1FFVB676E) receives its clocking from one of the xcvr PLLs in the quad (such as QPLL0), which may receive its clocking in turn from a RefClk signal input to the quad.

With the CDR operating in lock-to-reference mode (e.g., at 25GHz), it would seem that occasional incremental adjustments on precisely when the incoming serial data is sampled could be made by slowly shifting the phase of the supplied RefClk signal in to the quad.

Please confirm whether incremental control of when serial data sampling is performed could in fact be achieved using such an approach; or, if that might not reliably work, then why not.

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Moderator
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Registered: ‎07-30-2007

I'm still not sure I understand your goal but shifting the phase of the incoming clock slightly would slightly shift the sample point but it might also act as impulse to the PLL and cause the PLL to oscillate a bit.  It might take some time for this to settle but the end result would be a shift of the sample point.  But only if the reference clock was rooted to the same oscillator as the far end reference clock (synchronous to the RX).  You have to remember that there is no CDR when you are in lock to reference mode.  You basically have a reference clock and a PLL in that mode.  If the refclk isn't synchronous you would still get a shift of the sample point from where it would have sampled but it wouldn't be a stable sample point with respect to the incoming data.  




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Registered: ‎07-30-2007

Yes, that is what the CDR circuitry does when you aren't in lock to reference mode.  Lock to reference just stops the Phase interpolator adjustments and stays on one phase.  There is usually a reason that the automatic adjustment of the CDR will not work that is causing you to use a lock to reference/oversampling approach.  Sometimes it is used because the normal CDR will not lock fast enough and sometimes it is used because there are not enough transitions in the incoming data to keep the normal CDR working properly.  If you use RAW data instead of encoded data for instance there would not be enough transitions for a CDR to run properly.  

You can't use this approach without oversampling because you don't have the necessary feedback to tell you when you need to adjust the CDR and in which direction it needs to be adjusted.




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Explorer
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Registered: ‎07-10-2013

The question I raised was not whether data recovery could be successfully effected by using an xcvr RX operating in lock-to-reference mode by making changes to the externally-sourced RefClk input signal.

The question I raised was, with the RX in lock-to-reference mode, whether slowly shifting the phase of the supplied RefClk signal would successfully allow incremental adjustments to be made on precisely when the incoming serial data is being sampled by the CDR.

And, I'd also want to raise the same question with regard to xcvr TX.  Namely, with the TX in lock-to-reference mode, whether slowly shifting the phase of the supplied RefClk signal would successfully allow incremental adjustments to be made to the phase of the outgoing serial data.

Note that the changes to the RefClk phase would be expected to be made only occasionally, and would have a maximum range of no more than one input or output UI (40ps in the case of a 25GHz datarate).

Both the RX- and TX-related questions are essentially asking whether the clock signal handling inside the xcvr clocking and RX & TX blocks are pretty much as outlined in the product documentation, or whether certain not-disclosed-to-the-customer behaviors may occur regarding how clocking is actually handled, which would result in the approaches outlined above not working reliably or even at all.

 

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Registered: ‎07-30-2007

I'm still not sure I understand your goal but shifting the phase of the incoming clock slightly would slightly shift the sample point but it might also act as impulse to the PLL and cause the PLL to oscillate a bit.  It might take some time for this to settle but the end result would be a shift of the sample point.  But only if the reference clock was rooted to the same oscillator as the far end reference clock (synchronous to the RX).  You have to remember that there is no CDR when you are in lock to reference mode.  You basically have a reference clock and a PLL in that mode.  If the refclk isn't synchronous you would still get a shift of the sample point from where it would have sampled but it wouldn't be a stable sample point with respect to the incoming data.  




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